Control Registers; Qspi Ch.n Mode Register - Epson S1C31D50 Technical Manual

The QSPI provides DMA transfer request enable bits corresponding to each DMA transfer request flag shown
above for the number of DMA channels. A DMA transfer request is sent to the pertinent channel of the DMA con-
troller only when the DMA transfer request flag, of which DMA transfer has been enabled by the DMA transfer
request enable bit, is set. The receive buffer full and transmit buffer empty DMA transfer request flags also serve as
interrupt flags, therefore, both the DMA transfer request and the interrupt cannot be enabled at the same time. After
a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer requests from being
issued. For more information on the DMA control, refer to the "DMA Controller" chapter.

15.8 Control Registers

QSPI Ch.n Mode Register

Register name Bit
QSPI_nMOD 15–12 CHDL[3:0]
11–8 CHLN[3:0]
7–6 TMOD[1:0]
5
4
3
2
1
0
Bits 15–12 CHDL[3:0]
These bits set the number of clocks to drive the serial output data lines. This setting is required to out-
put the XIP confirmation bit to Micron Flash memories or to output the mode byte to Spansion Flash
memories.
These bits must be set to a value smaller than or equal to the QSPI_nMOD.CHLN[3:0] bit setting.
Note: When using the QSPI in slave mode, the QSPI_nMOD.CHDL[3:0] bits should be set to the
same value as the QSPI_nMOD.CHLN[3:0] bits.
Bits 11–8 CHLN[3:0]
These bits set the number of clocks for data transfer.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name Initial
0x7
0x7
0x0
PUEN 0
NOCLKDIV 0
LSBFST 0
CPHA 0
CPOL 0
MST 0
Table 15.8.1 Data Line Drive Length Settings
QSPI_nMOD.CHDL[3:0] bits
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko Epson Corporation
15 Quad Synchronous Serial Interface (QSPI)
Reset R/W
H0 R/W –
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
Data line drive length
16 clocks
15 clocks
14 clocks
13 clocks
12 clocks
11 clocks
10 clocks
9 clocks
8 clocks
7 clocks
6 clocks
5 clocks
4 clocks
3 clocks
2 clocks
1 clock
Remarks
15-29