Dmac Error Interrupt Enable Clear Register - Epson S1C31D50 Technical Manual

Bit 0 ERRIESET
This bit enables DMA error interrupts.
1 (W): Enable interrupt
0 (W): Ineffective
1 (R): Interrupt has been enabled.
0 (R): Interrupt has been disabled.

DMAC Error Interrupt Enable Clear Register

Register name Bit
DMACERRIECLR 31–24 –
23–16 –
15–8 –
7–1 –
0
Bits 31–1 Reserved
Bit 0 ERRIECLR
This bit disables DMA error interrupts.
1 (W): Disable interrupt (The DMACERRIESET register is cleared to 0.)
0 (W): Ineffective
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name Initial
0x00
0x00
0x00
0x00
ERRIECLR –
Seiko Epson Corporation
6 DMA CONTROLLER (DMAC)
Reset R/W
– R –
– R
– R
– R
– W
Remarks
6-15