Cache Controller (Cache) - Epson S1C31D50 Technical Manual

APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
Address Register name
0x0020 CLGOSC3
0048 (CLG OSC3 Control
Register)
0x0020 CLGINTF
004c (CLG Interrupt Flag
Register)
0x0020 CLGINTE
004e (CLG Interrupt Enable
Register)
0x0020 CLGFOUT
0050 (CLG FOUT Control
Register)
0x0020 0080
Address Register name
0x0020 CACHECTL
0080 (CACHE Control
Register)
0x0020 00a0–0x0020 00a4
Address Register name
0x0020 WDT2CLK
00a0 (WDT2 Clock Control
Register)
0x0020 WDT2CTL
00a2
(WDT2 Control
Register)
AP-A-2
Bit Bit name
15–12 –
11–10 OSC3FQ[1:0]
9 OSC3MD
8 –
7–6 –
5–4 OSC3INV[1:0]
3 OSC3STM
2–0 OSC3WT[2:0]
15–9 –
8 OSC3TERIF
7 –
6 (reserved)
5 OSC1STPIF
4 OSC3TEDIF
3 –
2 OSC3STAIF
1 OSC1STAIF
0 IOSCSTAIF
15–9 –
8 OSC3TERIE
7 –
6 (reserved)
5 OSC1STPIE
4 OSC3TEDIE
3 –
2 OSC3STAIE
1 OSC1STAIE
0 IOSCSTAIE
15–8 –
7 –
6–4 FOUTDIV[2:0]
3–2 FOUTSRC[1:0]
1 –
0 FOUTEN
Bit Bit name
15–8 –
7–2 –
1 –
0 CACHEEN
Bit Bit name
15–9 –
8 DBRUN
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
15–11 –
10–9 MOD[1:0]
8 STATNMI
7–5 –
4 WDTCNTRST
3–0 WDTRUN[3:0]
Seiko Epson Corporation
Initial Reset R/W
0x0 – R
0x1 H0 R/WP
0 H0 R/WP
0 – R
0x0 – R
0x3 H0 R/WP
0 H0 R/WP
0x6 H0 R/WP
0x00 – R
0 H0 R/W
0 – R
0 H0 R
0 H0 R/W
0 H0 R/W
0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0 H0 R/W
0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0 – R
0x0 H0 R/W
0x0 H0 R/W
0 – R
0 H0 R/W

Cache Controller (CACHE)

Initial Reset R/W
0x00 – R
0x00 – R
1 – R
0 H0 R/W
Watchdog Timer (WDT2)
Initial Reset R/W
0x00 – R
0 H0 R/WP
0x0 – R
0x0 H0 R/WP
0x0 – R
0x0 H0 R/WP
0x00 – R
0x0 H0 R/WP
0 H0 R
0x0 – R
0 H0 WP
0xa H0 R/WP –
S1C31D50/D51 TECHNICAL MANUAL
Remarks
–
–
Cleared by writing 1.
–
Cleared by writing 1.
–
Cleared by writing 1.
–
–
Remarks
–
Remarks
–
–
Always read as 0.
(Rev. 2.00)