Table of Contents
Advertisement
CONTENTS
DMAC Transfer Completion Interrupt Enable Set Register .................................................. 6-14
DMAC Transfer Completion Interrupt Enable Clear Register ............................................... 6-14
DMAC Error Interrupt Enable Set Register ........................................................................... 6-14
DMAC Error Interrupt Enable Clear Register ........................................................................ 6-15
7 I/O Ports (PPORT) .........................................................................................................7-1
7.1 Overview ......................................................................................................................... 7-1
7.2 I/O Cell Structure and Functions ..................................................................................... 7-2
7.2.1 Schmitt Input .......................................................................................................... 7-2
7.2.2 Over Voltage Tolerant Fail-Safe Type I/O Cell ........................................................ 7-3
7.2.3 Pull-Up/Pull-Down .................................................................................................. 7-3
7.2.4 CMOS Output and High Impedance State ............................................................. 7-3
7.3 Clock Settings ................................................................................................................. 7-3
7.3.1 PPORT Operating Clock......................................................................................... 7-3
7.3.2 Clock Supply in SLEEP Mode ................................................................................ 7-3
7.3.3 Clock Supply During Debugging ............................................................................ 7-4
7.4 Operations ...................................................................................................................... 7-4
7.4.1 Initialization ............................................................................................................. 7-4
7.4.2 Port Input/Output Control ...................................................................................... 7-5
7.5 Interrupts ......................................................................................................................... 7-6
7.6 Control Registers ............................................................................................................ 7-7
Px Port Data Register ............................................................................................................ 7-7
Px Port Enable Register ......................................................................................................... 7-7
Px Port Pull-up/down Control Register ................................................................................. 7-8
Px Port Interrupt Flag Register .............................................................................................. 7-8
Px Port Interrupt Control Register ......................................................................................... 7-8
Px Port Chattering Filter Enable Register .............................................................................. 7-9
Px Port Mode Select Register ............................................................................................... 7-9
Px Port Function Select Register........................................................................................... 7-9
P Port Clock Control Register .............................................................................................. 7-10
P Port Interrupt Flag Group Register .................................................................................... 7-11
7.7 Control Register and Port Function Configuration of this IC ......................................... 7-12
7.7.1 P0 Port Group ....................................................................................................... 7-12
7.7.2 P1 Port Group ....................................................................................................... 7-14
7.7.3 P2 Port Group ....................................................................................................... 7-17
7.7.4 P3 Port Group ....................................................................................................... 7-19
7.7.5 P4 Port Group ....................................................................................................... 7-21
7.7.6 P5 Port Group ....................................................................................................... 7-24
7.7.7 P6 Port Group ....................................................................................................... 7-26
7.7.8 P7 Port Group ....................................................................................................... 7-28
7.7.9 P8 Port Group ....................................................................................................... 7-31
7.7.10 P9 Port Group ..................................................................................................... 7-33
7.7.11 Pa Port Group ..................................................................................................... 7-35
7.7.12 Pd Port Group ..................................................................................................... 7-37
7.7.13 Common Registers between Port Groups .......................................................... 7-39
8 Universal Port Multiplexer (UPMUX) ...........................................................................8-1
8.1 Overview ......................................................................................................................... 8-1
8.2 Peripheral Circuit I/O Function Assignment .................................................................... 8-1
8.3 Control Registers ............................................................................................................ 8-2
Pxy-xz Universal Port Multiplexer Setting Register ............................................................... 8-2
9 Watchdog Timer (WDT2) ..............................................................................................9-1
9.1 Overview ......................................................................................................................... 9-1
9.2 Clock Settings ................................................................................................................. 9-1
iv
Seiko Epson Corporation
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Advertisement
Table of Contents
