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15 Quad Synchronous Serial Interface (QSPI)
QSPI_nMOD register
CPOL bit
CPHA bit
1
1
0
0
Figure 15.5.6.5 Data Receiving Operation in Memory Mapped Access Mode - 8/16-bit Sequential Read
15-22
HCLK
HSEL
HADDR
n
HTRANS
2
HSIZE
0/1
HREADY
HRDATA
QSPICLKn
QSDIOn[3:0]
Seiko Epson Corporation
Data cycle
S1C31D50/D51 TECHNICAL MANUAL
n
(Rev. 2.00)
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