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2 POWER SUPPLY, RESET, AND CLOCKS
2.1.3 V
Regulator Operation Mode
D1
The V
regulator supports two operation modes, normal mode and economy mode. Setting the V
D1
economy mode at light loads helps achieve low-power operations. Table 2.1.3.1 lists examples of light load condi-
tions in which economy mode can be set.
Table 2.1.3.1 Examples of Light Load Conditions in which Economy Mode Can be Set
SLEEP mode (when all oscillators are stopped, or OSC1 only is active) When a clock source except for
HALT mode (when OSC1 only is active)
RUN mode (when OSC1 only is active)
The V
regulator also supports automatic mode in which the hardware detects a light load condition and automati-
D1
cally switches between normal mode and economy mode. Use the V
control is required.
2.1.4 V
Regulator Voltage Mode
D1
The V
regulator supports two voltage modes, mode0 and mode1.
D1
When the IC runs with a low-speed clock, setting the V
When the voltage mode is switched, the system clock source automatically stops operating and it resumes operating
after the voltage has stabilized. Table 2.1.4.1 shows the stop period of the system clock.
Table 2.1.4.1 System Clock Stop Period After Switching Voltage Mode
System clock
IOSC
OSC1
Procedure to switch from mode0 to mode1
1. Set the MODEN bits of the peripheral circuits to 0.
2. Write 0x0096 to the SYSPROT.PROT[15:0] bits.
3. Switch the system clock to a low-speed clock (OSC1, IOSC 1.8 MHz or 0.9 MHz).
4. Stop OSC3 and EXOSC.
5. Configure the following PWGACTL register bits.
- Set the PWGACTL.REGSEL bit to 0.
- Set the PWGACTL.REGDIS bit to 1.
- Set the PWGACTL.REGMODE[1:0] bits to 0x2.
6. Configure the following PWGACTL register bits after the system clock supply has resumed.
- Set the PWGACTL.REGDIS bit to 0.
- Set the PWGACTL.REGMODE[1:0] bits to 0x0.
7. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection)
Procedure to switch from mode1 to mode0
1. Set the MODEN bits of the peripheral circuits to 0.
2. Write 0x0096 to the SYSPROT.PROT[15:0] bits.
3. Configure the following PWGACTL register bits.
- Set the PWGACTL.REGSEL bit to 1.
- Set the PWGACTL.REGMODE[1:0] bits to 0x2.
4. Set the PWGACTL.REGMODE[1:0] bits to 0x0
after the system clock supply has resumed.
5. Switch the system clock to a high-speed clock.
6. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection)
2-2
Light load condition
D1
Number of cycles set using the CLGOSC1.OSC1WT[1:0] bits
Seiko Epson Corporation
OSC1 is active
regulator in automatic mode when no special
D1
regulator into mode1 reduces power consumption.
Stop period
4,096 cycles
(Stop using peripheral circuits)
(Remove system protection)
(Switch to mode1)
(Discharge)
(Set to normal mode)
(Stop discharging)
(Set to automatic mode)
(Stop using peripheral circuits)
(Remove system protection)
(Switch to mode0)
(Set to normal mode)
(Set to automatic mode)
S1C31D50/D51 TECHNICAL MANUAL
regulator into
D1
Exceptions
(Rev. 2.00)
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