Vector Table Offset Address (Vtor); Priority Of Interrupts; Peripheral Circuit Interrupt Control - Epson S1C31D50 Technical Manual

Interrupt IRQ Vector
number number address
37 21 VTOR + 0x90 Synchronous serial interface
38 22 VTOR + 0x98 16-bit timer Ch.4 interrupt
39 23 VTOR + 0x9c 16-bit timer Ch.5 interrupt
40 24 VTOR + 0xa0 16-bit timer Ch.6 interrupt
41 25 VTOR + 0xa4 R/F converter Ch.0 interrupt
42 26 VTOR + 0xa8 12-bit A/D converter interrupt • Analog input signal m A/D conversion
43 27 VTOR + 0xac Synchronous serial interface
44 28 VTOR + 0xb0 I
45 29 VTOR + 0xb4 IR remote controller interrupt • Compare AP
46–47 – –
*1 Either reset or NMI can be selected as the watchdog timer interrupt via software.

5.2.1 Vector Table Offset Address (VTOR)

The CPU core provides the vector table offset register to set the offset (start) address of the vector table in which
interrupt vectors are programmed. "VTOR" described in Table 5.2.1 means the value set to this register. After an
initial reset, VTOR is set to address 0x0. Therefore, even when the vector table location is changed, it is necessary
that at least the reset vector be written to this address. For more information on VTOR, refer to the "Cortex
Technical Reference Manual."

5.2.2 Priority of Interrupts

The priorities of SVCall, PendSV, and SysTick are configurable to the desired levels using the System Handler
Priority Registers (SHPR2 and SHPR3). The priorities of the interrupt number 16 or later are configurable to the
desired levels using the Interrupt Priority Registers (NVIC_IPR0–7). The priority value can be set within a range of
0 to 192 (a lower value has a higher priority). The priorities of reset, NMI, and HardFault are fixed at the predefined
values. For more information, refer to the "Cortex

5.3 Peripheral Circuit Interrupt Control

The peripheral circuit that generates interrupts includes an interrupt enable bit and an interrupt flag for each inter-
rupt cause.
Interrupt flag: The flag is set to 1 when the interrupt cause occurs. The clear condition depends on the periph-
eral circuit.
Interrupt enable bit: By setting this bit to 1 (interrupt enabled), an interrupt request will be sent to the CPU core
when the interrupt flag is set to 1. When this bit is set to 0 (interrupt disabled), no interrupt
request will be sent to the CPU core even if the interrupt flag is set to 1. An interrupt request is
also sent to the CPU core if the status is changed to interrupt enabled when the interrupt flag is 1.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Hardware interrupt name
Ch.1 interrupt
Ch.2 interrupt
16-bit timer Ch.7 interrupt
2
C Ch.2 interrupt
Reserved
® -M0+ Technical Reference Manual."
Seiko Epson Corporation
Cause of hardware interrupt
• End of transmission
• Receive buffer full
• Transmit buffer empty
• Overrun error
Underflow
Underflow
Underflow
• Reference oscillation completion
• Sensor A oscillation completion
• Sensor B oscillation completion
• Measurement counter overflow error
• Time base counter overflow error
completion
• Analog input signal m A/D conversion result
overwrite error
• End of transmission
• Receive buffer full
• Transmit buffer empty
• Overrun error
Underflow
• End of data transfer
• General call address reception
• NACK reception
• STOP condition
• START condition
• Error detection
• Receive buffer full
• Transmit buffer empty
• Compare DB
–
5 INTERRUPT
Priority
® -M0+
5-3