Epson S1C31D50 Technical Manual page 40

2 POWER SUPPLY, RESET, AND CLOCKS
SLEEP mode
When the Cortex ® -M0+ core executes the WFI or WFE instruction with the SLEEPDEEP bit of the system
control register set to 1, it suspends program execution and stops operating. This state is referred to SLEEP
mode in this IC. In this mode, the clock sources stop operating as well.
However, the clock source in which the CLGOSC.IOSCSLPC/OSC1SLPC/OSC3SLPC/EXOSCSLPC bit is set
to 0 keeps operating, so the peripheral circuits with the clock being supplied can also operate. By setting this
mode when no software processing and peripheral circuit operations are required, power consumption can be
less than HALT mode.
Transition takes place automatically by the
initial boot sequence after a request from
the reset source is canceled.
OSC1
HALT
OSC1
RUN
CLGSCLK.CLKSRC[1:0] = 0x3
Figure 2.4.2.1 Operating Mode-to-Mode State Transition Diagram
Canceling HALT or SLEEP mode
The conditions listed below generate the HALT/SLEEP cancelation signal to cancel HALT or SLEEP mode and
put the CPU into RUN mode.
• Interrupt request from a peripheral circuit
• NMI from the watchdog timer
• Reset request
2-14
RESET
(Initial state)
IOSC
RUN
CLGSCLK.CLKSRC[1:0] = 0x1
OSC3
RUN
OSC3
HALT
Seiko Epson Corporation
WFI/WFE instruction
IOSC
RUN
HALT
EXOSC
RUN
∗ In RUN and HALT modes, the clock sources not used
as SYSCLK can be all disabled.
S1C31D50/D51 TECHNICAL MANUAL
(SLEEPDEEP = 1)
SLEEP
HALT/SLEEP
cancelation signal
(wake-up)
EXOSC
HALT
(Rev. 2.00)