Power Supply, Reset, And Clocks; Power Generator (Pwga); Overview; Pins - Epson S1C31D50 Technical Manual

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2 Power Supply, Reset, and Clocks

The power supply, reset, and clocks in this IC are managed by the embedded power generator, system reset control-
ler, and clock generator, respectively.

2.1 Power Generator (PWGA)

2.1.1 Overview

PWGA is the power generator that controls the internal power supply system to drive this IC with stability and low
power. The main features of PWGA are outlined below.
• Embedded V
regulator
D1
- The V
regulator generates the V
D1
consumption constant independent of the V
- The V
regulator supports two operation modes, normal mode and economy mode, and setting the V
D1
lator into economy mode at light loads helps achieve low-power operations.
- The V
regulator supports two voltage modes, mode0 and mode1, and setting the V
D1
during low-speed operation helps achieve low-power operations.
Figure 2.1.1.1 shows the PWGA configuration.
C
PW1
C
PW2
V
DD
or
another external
power supply

2.1.2 Pins

Table 2.1.2.1 lists the PWGA pins.
Pin name
I/O
Initial status
V
P
DD
V
P
SS
V
A
D1
V
P
DDQSPI
For the V
/V
operating voltage ranges and recommended external parts, refer to "Recommended Operating
DD
DDQSPI
Conditions, Power supply voltage V
Connection Diagram" chapter, respectively.
V
DDQSPI
V
is the power supply dedicated for the quad synchronous serial interface (QSPI-Flash). It is also used as
DDQSPI
the power supply for the I/O ports P90 to P95.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
voltage to drive internal circuits, this makes it possible to keep current
D1
voltage level.
DD
PWGA
REGMODE[1:0]
V
DD
V
D1
V
SS
V
DDQSPI
C
VDDQSPI
Figure 2.1.1.1 PWGA Configuration
Table 2.1.2.1 List of PWGA Pins
Power supply (+)
GND
V
regulator output pin
D1
QSPI interface (QSPI-Flash) and I/O power supply (for P9 port group)
/V
" in the "Electrical Characteristics" chapter and the "Basic External
DD
DDQSPI
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
REGSEL
V
D1
V
D1
regulator
REGDIS
Function
regu-
D1
regulator into mode1
D1
Internal circuits
I/O ports
(except for P9 port groups)
Quad synchronous serial
interface and I/O ports
(P9 port group)
2-1

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