Uart3 Ch.n Interrupt Enable Register - Epson S1C31D50 Technical Manual

Bit 6 TENDIF
Bit 5 FEIF
Bit 4 PEIF
Bit 3 OEIF
Bit 2 RB2FIF
Bit 1 RB1FIF
Bit 0 TBEIF
These bits indicate the UART3 interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
The following shows the correspondence between the bit and interrupt:
UART3_nINTF.TENDIF bit: End-of-transmission interrupt
UART3_nINTF.FEIF bit:
UART3_nINTF.PEIF bit:
UART3_nINTF.OEIF bit:
UART3_nINTF.RB2FIF bit: Receive buffer two bytes full interrupt
UART3_nINTF.RB1FIF bit: Receive buffer one byte full interrupt
UART3_nINTF.TBEIF bit:

UART3 Ch.n Interrupt Enable Register

Register name Bit
UART3_nINTE 15–8 –
7
6
5
4
3
2
1
0
Bits 15–7 Reserved
Bit 6 TENDIE
Bit 5 FEIE
Bit 4 PEIE
Bit 3 OEIE
Bit 2 RB2FIE
Bit 1 RB1FIE
Bit 0 TBEIE
These bits enable UART3 interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
The following shows the correspondence between the bit and interrupt:
UART3_nINTE.TENDIE bit: End-of-transmission interrupt
UART3_nINTE.FEIE bit:
UART3_nINTE.PEIE bit:
UART3_nINTE.OEIE bit:
UART3_nINTE.RB2FIE bit: Receive buffer two bytes full interrupt
UART3_nINTE.RB1FIE bit: Receive buffer one byte full interrupt
UART3_nINTE.TBEIE bit: Transmit buffer empty interrupt
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Framing error interrupt
Parity error interrupt
Overrun error interrupt
Transmit buffer empty interrupt
Bit name Initial
0x00
– 0
TENDIE 0
FEIE 0
PEIE 0
OEIE 0
RB2FIE 0
RB1FIE 0
TBEIE 0
Framing error interrupt
Parity error interrupt
Overrun error interrupt
Seiko Epson Corporation
Reset R/W
– R –
– R
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
13 UART (UART3)
Remarks
13-15