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Peripheral circuit
12-bit A/D converter
(ADC12A) Ch.0
R/F converter (RFC) Ch.0
Sound DAC (SDAC)
HW processor (HWP)
DMA controller (DMAC)
4.5.1 System-Protect Function
The system-protect function protects control registers and bits from writings. They cannot be rewritten unless write
protection is removed by writing 0x0096 to the SYSPROT.PROT[15:0] bits. This function is provided to prevent
deadlock that may occur when a system-related register is altered by a runaway CPU. See "Control Registers" in
each peripheral circuit to identify the registers and bits with write protection.
Note: Once write protection is removed using the SYSPROT.PROT[15:0] bits, write enabled status is
maintained until write protection is applied again. After the registers/bits required have been al-
tered, apply write protection.
4.6 Instruction Cache
This IC includes an instruction cache. Enabling the cache function translates into reduced current consumption, as
the Flash memory access frequency is decreased.
This function is enabled by setting the CASHECTL.CACHEEN bit to 1. Setting this bit to 0 clears the instruction
codes stored in the cache.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Address
0x0020 07b6 ADC12A_0DMAEN5 ADC12A Ch.0 DMA Request Enable Register 5
0x0020 07b8 ADC12A_0DMAEN6 ADC12A Ch.0 DMA Request Enable Register 6
0x0020 07ba ADC12A_0DMAEN7 ADC12A Ch.0 DMA Request Enable Register 7
0x0020 07bc ADC12A_0ADD
0x0020 0840 RFC_0CLK
0x0020 0842 RFC_0CTL
0x0020 0844 RFC_0TRG
0x0020 0846 RFC_0MCL
0x0020 0848 RFC_0MCH
0x0020 084a RFC_0TCL
0x0020 084c RFC_0TCH
0x0020 084e RFC_0INTF
0x0020 0850 RFC_0INTE
0x0020 0860 SDACCLK
0x0020 0862 SDACCTL
0x0020 0864 SDACMOD
0x0020 0866 SDACDAT
0x0020 0868 SDACINTF
0x0020 086a SDACINTE
0x0020 08a2 HWPCTL
0x0020 08a4 HWPINTF
0x0020 08a6 HWPINTE
0x0020 08a8 HWPCMDTRG
0x0020 1000 DMACSTAT
0x0020 1004 DMACCFG
0x0020 1008 DMACCPTR
0x0020 100c DMACACPTR
0x0020 1014 DMACSWREQ
0x0020 1020 DMACRMSET
0x0020 1024 DMACRMCLR
0x0020 1028 DMACENSET
0x0020 102c DMACENCLR
0x0020 1030 DMACPASET
0x0020 1034 DMACPACLR
0x0020 1038 DMACPRSET
0x0020 103c DMACPRCLR
0x0020 104c DMACERRIF
0x0020 2000 DMACENDIF
0x0020 2008 DMACENDIESET
0x0020 200c DMACENDIECLR
0x0020 2010 DMACERRIESET
0x0020 2014 DMACERRIECLR
Seiko Epson Corporation
Register name
ADC12A Ch.0 Result Register
RFC Ch.0 Clock Control Register
RFC Ch.0 Control Register
RFC Ch.0 Oscillation Trigger Register
RFC Ch.0 Measurement Counter Low Register
RFC Ch.0 Measurement Counter High Register
RFC Ch.0 Time Base Counter Low Register
RFC Ch.0 Time Base Counter High Register
RFC Ch.0 Interrupt Flag Register
RFC Ch.0 Interrupt Enable Register
SDAC Clock Control Register
SDAC Control Register
SDAC Mode Register
SDAC Data Register
SDAC Interrupt Flag Register
SDAC Interrupt Enable Register
HWP Control Register
HWP Interrupt Flag Register
HWP Interrupt Enable Register
HWP Command Trigger Register
DMAC Status Register
DMAC Configuration Register
DMAC Control Data Base Pointer Register
DMAC Alternate Control Data Base Pointer Register
DMAC Software Request Register
DMAC Request Mask Set Register
DMAC Request Mask Clear Register
DMAC Enable Set Register
DMAC Enable Clear Register
DMAC Primary-Alternate Set Register
DMAC Primary-Alternate Clear Register
DMAC Priority Set Register
DMAC Priority Clear Register
DMAC Error Interrupt Flag Register
DMAC Transfer Completion Interrupt Flag Register
DMAC Transfer Completion Interrupt Enable Set Register
DMAC Transfer Completion Interrupt Enable Clear Register
DMAC Error Interrupt Enable Set Register
DMAC Error Interrupt Enable Clear Register
4 MEMORY AND BUS
4-9
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