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2. This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson dose not assume any responsibility or liability of any kind of damage and/or fire coursed by the use of it.
PREFACE Preface This is a technical manual for designers and programmers who develop a product using the S1C17W12/W13. This document describes the functions of the IC, embedded peripheral circuit operations, and their control methods. For the CPU functions and instructions, refer to the “S1C17 Family S1C17 Core Manual.” For the functions and operations of the debugging tools, refer to the respective tool manuals.
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B.1 Operating Status Configuration Examples for Power Saving ........AP-B-1 B.2 Other Power Saving Methods ..................AP-B-2 Appendix C Mounting Precautions ................AP-C-1 Appendix D Measures Against Noise ................ AP-D-1 Appendix E Initialization Routine ................AP-E-1 Revision History Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
1 OVERVIEW 1 Overview The S1C17W12/W13 is a 16-bit MCU that features low-voltage operation from 1.2 V even though Flash memory is included. The embedded high-efficiency DC-DC converter generates the constant-voltage to drive the IC with lower power consumption than 4-bit MCUs. This IC includes a real-time clock, a stopwatch, an LCD driver, and a PWM timer capable of being used to generate drive waveforms for a motor driver as well as a high-performance 16-bit CPU.
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Flash 2.4 to 3.6 V (V = 7.5 V external power supply is required.) programming operating voltage for super – 2.5 to 3.6 V – 2.5 to 3.6 V economy mode Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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QFP13-64PIN (P-LQFP064-1010-0.50, 10 × 10 mm, t = 1.7 mm, 0.5 mm pitch) – TQFP12-48PIN (P-TQFP048-0707-0.50, 7 × 7 mm, t = 1.2 mm, 0.5 mm pitch) *1 Shown in parentheses are JEITA package names. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
16-bit PWM timer CAP00–01 IR remote (T16B) controller CAP10–11 REMO 2 Ch. (REMC2) EXCL00–01 CLPLS 1 Ch. EXCL10–11 *1 These pins do not exist in the SQFN7-48PIN package. Figure 1.2.1 S1C17W12 Block Diagram Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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2 Ch. EXCL00–01 (REMC2) CLPLS 1 Ch. EXCL10–11 *1 These pins do not exist in the TQFP12-48PIN package. *2 These pins do not exist in the SQFN7-48PIN package. Figure 1.2.2 S1C17W13 Block Diagram Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
P23/UPMUX/SEG11 P00/REMO/UPMUX P24/UPMUX/SEG10 P25/UPMUX/SEG9 P26/UPMUX/SEG8 Figure 1.3.1.1 S1C17W12 Pin Configuration Diagram (SQFN7-48PIN) Note: The model in this package cannot be placed into super economy mode, as it does not have the , and C pins. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL...
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P25/UPMUX/SEG9 P26/UPMUX/SEG8 Figure 1.3.1.3 S1C17W13 Pin Configuration Diagram (SQFN7-48PIN) Note: The model in this package cannot be placed into super economy mode, as it does not have the , and C pins. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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P25/UPMUX/SEG9 P26/UPMUX/SEG8 Figure 1.3.1.4 S1C17W13 Pin Configuration Diagram (TQFP12-48PIN) Note: The model in this package cannot be placed into super economy mode, as it does not have the , and C pins. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
P22/UPMUX/SEG12 P23/UPMUX/SEG11 P24/UPMUX/SEG10 P25/UPMUX/SEG9 P26/UPMUX/SEG8 Die No. CJxxxxx 2.300 mm Figure 1.3.2.1 S1C17W12/W13 Pad Configuration Diagram (Chip) Pad opening: X = 68 µm, Y = 68 µm Chip thickness: 400 µm 3.2.1 S1C17W12/W13 Pad Coordinates X µm Y µm X µm Y µm...
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TOUTn0/CAPn0 n = 0, 1 T16B Ch.n PWM output/capture input 0 (T16B) TOUTn1/CAPn1 T16B Ch.n PWM output/capture input 1 Note: Do not assign a function to two or more pins simultaneously. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 1-13 (Rev. 1.2)
Power supply voltage V ” in the “Electrical Characteristics” chapter and the “Basic External Connection Dia- gram” chapter, respectively. Note: Be sure to avoid using the V and V pin outputs for driving external circuits. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
PWGINTF.MODCMPIF bit to 1. 2. When a clock source other than OSC1 is started in economy mode The hardware switches to normal mode at the same time the clock source is started. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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(or economy mode). Do not perform heavy- load operations, such as starting a high-speed clock source, before the PWGINTF.MODC- MPIF bit is set to 1, as it may cause a malfunction. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
The reset source refers to causes that request system initialization. The following shows the reset sources. #RESET pin Inputting a reset signal with a certain low level period to the #RESET pin issues a reset request. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Watchdog timer reset #RESET pin Peripheral circuit software reset Reset state is canceled immediately (MODEN and SFTRST bits. The after the reset request is canceled. software reset operations de- pend on the peripheral circuit. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
- The oscillator and clock input circuit on/off state can be maintained or changed at SLEEP mode cancelation. • Provides the FOUT function to output an internal clock for driving external ICs or for monitoring the internal state. Figure 2.3.1.1 shows the CLG configuration. Table 2.3.1.1 CLG Configuration of S1C17W12/W13 S1C17W12 S1C17W13 Item...
For more information on the auto-trimming function and the oscillation characteristics, refer to “IOSC oscillation auto- trimming function” in this chapter and “IOSC oscillator circuit characteristics” in the “Electrical Characteris- tics” chapter, respectively. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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Figure 2.3.3.2 OSC1 Oscillator Circuit Configuration For the recommended parts and the oscillation characteristics, refer to the “Basic External Connection Dia- gram” chapter and “OSC1 oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respec- tively. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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“Electrical Characteristics” chapter, respectively. EXOSC clock input EXOSC is an external clock input circuit that supports square wave and sine wave clocks. Figure 2.3.3.4 shows the configuration of the EXOSC clock input circuit. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Furthermore, the oscillation start time being actually reduced depends on the characteristics of the resonator used. Figure 2.3.4.2 shows an operation example when the oscillation startup control circuit is used. Seiko Epson Corporation 2-10 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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7. OSC1CLK can be used if the CLGINTF.OSC1STAIF bit = 1 after an interrupt occurs. The setting values of the CLGOSC1.INV1N[1:0], CLGOSC1.CGI1[2:0], CLGOSC1.OSC1WT[1:0], and CLGOSC1.INV1B[1:0] bits should be determined after performing evaluation using the populated circuit board. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 2-11 (Rev. 1.2)
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SLEEP mode and RUN mode, and the peripheral circuits to continue operating without disabling the clock in SLEEP mode. The CLGOSC.IOSCSLPC, CLGOSC.OSC1SLPC, CLGOSC.OSC3SLPC, and CLGOSC.EXOSCSLPC bits are used for this control. Figure 2.3.4.3 shows a control example. Seiko Epson Corporation 2-12 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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2. Configure the following CLGFOUT register bits: - CLGFOUT.FOUTSRC[1:0] bits (Select clock source) - CLGFOUT.FOUTDIV[2:0] bits (Set clock division ratio) - Set the CLGFOUT.FOUTEN bit to 1. (Enable clock external output) Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 2-13 (Rev. 1.2)
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7. The OSC1 oscillation stops if the CLGINTF.OSC1STPIF bit = 1 after an interrupt occurs. If the CLGOSC1.OSDRB bit = 1, the hardware restarts the OSC1 oscillator circuit. Note: Enabling the oscillation stop detection function increase the oscillation stop detector current OSD1 Seiko Epson Corporation 2-14 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
When a debug interrupt occurs, the CPU enters DEBUG mode. DEBUG mode is canceled when the retd in- struction is executed. For more information on DEBUG mode, refer to “Debugger” in the “CPU and Debugger” chapter. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 2-15 (Rev. 1.2)
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CPU into RUN mode. This transition is executed even if the CPU does not accept the interrupt request. • Interrupt request from a peripheral circuit • NMI from the watchdog timer • Debug interrupt • Reset request Seiko Epson Corporation 2-16 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Operating mode 0x7–0x6 Reserved Super economy mode Reserved Economy mode Normal mode Reserved Automatic mode Note: The PWGCTL.PWGMOD[2:0] bits are set to 0x0 when 0x7, 0x6, 0x4, or 0x1 is written. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 2-17 (Rev. 1.2)
This bit selects an oscillator type of the OSC1 oscillator circuit. 1 (R/WP): Internal oscillator 0 (R/WP): Crystal oscillator Bits 10–8 CGI1[2:0] These bits set the internal gate capacitance in the OSC1 crystal oscillator circuit. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 2-21 (Rev. 1.2)
Note: The CLGINTF.IOSCSTAIF bit is 0 after system reset is canceled, but IOSCCLK has already been stabilized. CLG Interrupt Enable Register Register name Bit name Initial Reset Remarks CLGINTE 15–8 – 0x00 – – – – (reserved) OSC1STPIE IOSCTEDIE – – OSC3STAIE OSC1STAIE IOSCSTAIE Seiko Epson Corporation 2-24 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
1/256 1/16 Reserved Reserved Reserved Reserved Note: When the CLGFOUT.FOUTSRC[1:0] bits are set to 0x3, the FOUT output will be stopped in SLEEP/HALT mode as SYSCLK is stopped. Bit 1 Reserved Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 2-25 (Rev. 1.2)
Be aware that the frequency characteristics may not be sat- isfied when these settings are altered. When altering these settings, always make sure that the relevant oscillator circuit is inactive. Seiko Epson Corporation 2-26 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
3 CPU AND DEBUGGER 3 CPU and Debugger 3.1 Overview This IC incorporates the Seiko Epson original 16-bit CPU core (S1C17) with a debugger. The main features of the CPU core are listed below. • Seiko Epson original 16-bit RISC processor...
DBRUN bit, refer to “Clock Supply in DEBUG Mode” in each peripheral circuit chapter. DE- BUG mode continues until a cancel command is sent from the personal computer or the CPU executes the retd in- struction. Neither hardware interrupts nor NMI are accepted during DEBUG mode. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, DSIO pull-up resis- tor R ” in the “Electrical Characteristics” chapter. R is not required when using the DSIO pin as a general- purpose I/O port pin. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
The value (0 or 1) of the PSR Z (zero) flag can be read out with this bit. Bit 0 PSRN The value (0 or 1) of the PSR N (negative) flag can be read out with this bit. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
– 23–0 DBRAM[23:0] *1 Debugging work area start address Bits 31–24 Reserved Bits 23–0 DBRAM[23:0] The start address of the debugging work area (64 bytes) can be read out with these bits. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Access size designated by the CPU instructions (e.g., ld %rd, [%rb] → 16-bit data transfer) Table 4.2.1 lists numbers of bus access cycles by different device size and access size. The peripheral circuits can be accessed with an 8-bit, 16-bit, or 32-bit instruction. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
The number of bus access cycles for reading can be configured using the FLASHCWAIT.RDWAIT[1:0] bits. Select a setting for higher frequency than the system clock. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
The embedded display data RAM is used to store display data for the LCD driver. Areas unused for display data in the display data RAM can be used as a general-purpose RAM. For specific information on the display data RAM, refer to “Display Data RAM” in the “LCD Driver” chapter. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
0x544e RFC0INTF RFC Ch.0 Interrupt Flag Register 0x5450 RFC0INTE RFC Ch.0 Interrupt Enable Register *1 Not available in the S1C17W12 SQFN7-48PIN package *2 Not available in the S1C17W13 SQFN7-48PIN package *3 Not available in the S1C17W13 TQFP12-48PIN package 4.6.1 System-Protect Function The system-protect function protects control registers and bits from writings.
FLASHCWAIT.RDWAIT[1:0] bits Number of bus Access cycles System clock frequency 4.2 MHz (max.) 4.2 MHz (max.) 4.2 MHz (max.) 2.1 MHz (max.) Note: Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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– ↓ 31 (0x1f) TTBR + 0x7c reserved – *1 When the same interrupt level is set *2 Either reset or NMI can be selected as the watchdog timer interrupt with software. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
ITC simultaneously from two or more peripheral circuits. • The interrupt with the highest interrupt level takes precedence. • If multiple interrupt requests are input with the same interrupt level, the interrupt with the lowest vector number takes precedence. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Note: When HALT or SLEEP mode is canceled, the CPU jumps to the interrupt handler routine after executing one instruction. To execute the interrupt handler routine immediately after HALT or SLEEP mode is canceled, place the nop instruction at just behind the halt/slp instruction. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Note: ‘x’, which is used in the port names Pxy, register names, and bit names, refers to a port group (x = 0, 1, 2, ··· , d) and ‘y’ refers to a port number (y = 0, 1, 2, ··· , 7). Figure 6.1.1 shows the configuration of PPORT. Table 6.1.1 Port Configuration of S1C17W12/W13 S1C17W12 S1C17W13...
Analog control signal Analog control signal Over voltage tolerant fail-safe type I/O cell Standard I/O cell Output signal Output control signal I/O cell for LED drive pin Figure 6.2.1 I/O Cell Configuration Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
The I/O cell for the LED drive pin is formed as an Nch open drain type structure that allows directly driving of an LED. This pin supports an output function only, so it does not allow software to perform input control and pull-up/ down control. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
• Port pins: High impedance state • Port function: Configured to GPIO This status continues until the ports are configured via software. The debugging function ports are configured for debug signal input/output. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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* Steps 1 and 5 are required for the ports with an interrupt function. Step 2 is required for the ports with a chat- tering filter function. Table 6.4.1.1 lists the port status according to the combination of data input/output control and pull-up/down control. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
2. Configure the input pin combination for key-entry reset using the PCLK.KRSTCFG[1:0] bits. Note: When enabling the key-entry reset function, be sure to configure the port pins to be used for it as general-purpose input pins before setting the PCLK.KRSTCFG[1:0] bits. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
(PxIOEN.PxOENy bit = 0), it does not affect the pin status. These bits do not affect the outputs when the port is used as a peripheral I/O function. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
PxIOEN.PxIENy bit is set and the port is not pulled up/down. These bits do not affect the pull-up/down control when the port is used as a peripheral I/O function. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
PxMODSEL 15–8 – 0x00 – – 7–0 PxSEL[7:0] 0x00 *1: The bit configuration differs depending on the port group. *2: The initial value may be changed by the port. Bits 15–8 Reserved Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
A port generated an interrupt 0 (R): No port generated an interrupt The PINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt is cleared. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 6-11 (Rev. 1.2)
6.7.5 P4 Port Group The P4 port group consists of four ports P40–P43 and they support the GPIO function. Note: The P4 port group does not exist in the S1C17W12 SQFN7-48PIN, S1C17W13 TQFP12-48PIN, and SQFN7-48PIN packages. Table 6.7.5.1 Control Registers for P4 Port Group...
These five ports support the GPIO function. The GPIO function of the Pd2 port supports out- put only, therefore, the pull-up/down function cannot be used. Note: The Pd3 and Pd4 ports do not exist in the SQFN7-48PIN package of the S1C17W12 and S1C17W13.
4. Initialize the peripheral circuit. 5. Set the PxFNCSEL.PxyMUX[1:0] bits of the I/O port to 0x1. (Select peripheral I/O function 1) 6. Set the PxMODSEL.PxSELy bit of the I/O port to 1. (Enable peripheral I/O function) Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Note: Do not assign a peripheral input function to two or more I/O ports. Although the I/O ports output the same waveforms when an output function is assigned to two or more I/O port, a skew oc- curs due to the internal delay. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
CLK_WDT2 supply is suspended, the register retains the status before DEBUG mode was entered. If the WDTCLK.DBRUN bit = 1, the CLK_WDT2 supply is not suspended and WDT2 will keep operating in DE- BUG mode. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection) 2. Write 0xa to the WDTCTL.WDTRUN[3:0] bits. (Stop WDT2) 3. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection) Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
IOSC OSC1 OSC3 EXOSC 1/16,384 1/128 1/16,384 1/8,192 1/8,192 1/4,096 1/4,096 1/2,048 1/2,048 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Always 0x0 is read if a value other than 0xa is written. Since an NMI or reset may be generated immediately after running depending on the counter value, WDT2 should also be reset concurrently when running WDT2. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
These bits set the NMI/reset generation cycle. The value set in this register is compared with the 10-bit counter value while WDT2 is running, and an NMI or reset is generated when they are matched. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
* Indicates the status when the pin is configured for RTCA. If the port is shared with the RTCA output function and other functions, the RTCA function must be assigned to the port. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
3. Write 1 to the RTCINTF.ALARMIF bit to clear the alarm interrupt flag. 4. Write 1 to the RTCINTE.ALARMIE bit to enable alarm interrupts. When the real-time clock counter reaches the alarm time set in Step 2, an alarm interrupt occurs. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
9.4.4 Stopwatch Count-up Pattern The stopwatch consists of 1/100-second and 1/10-second counters and these counters perform counting up in incre- ments of approximate 1/100 and 1/10 seconds with the count-up patterns shown in Figure 9.4.4.1. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
1 Hz counter value. • An alarm interrupt occurs after a lapse of 1/256 second from matching between the AM/PM (in 12H mode), hour, minute, and second counter value and the alarm setting value. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Depending on these operation timings, the +1 second correction may be executed after the count-up operation resumes. For more information on the +1 second correction, refer to “Real-Time Clock Counter Operations.” Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
The RTCALM1.RTCSHA[2:0] bits and the RTCALM1.RTCSLA[3:0] bits set the 10-second digit and 1-second digit of the alarm time, respectively. A value within 0 to 59 seconds can be set in BCD code as shown in Table 9.6.1. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
SWRUN Bits 15–12 BCD10[3:0] Bits 11–8 BCD100[3:0] The 1/10-second and 1/100-second digits of the stopwatch counter can be read as a BCD code from the RTCSWCTL.BCD10[3:0] bits and the RTCSWCTL.BCD100[3:0] bits, respectively. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
1-second digit of the second counter, respectively. The setting/read values are a BCD code within the range from 0 to 59. Note: Be sure to avoid writing to the RTCSEC.RTCSH[2:0]/RTCSL[3:0] bits while the RTCCTL. RTCBSY bit = 1. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
1 to 12 in 12H mode or 0 to 23 in 24H mode. Note: Be sure to avoid writing to the RTCHUR.RTCHH[1:0]/RTCHL[3:0] bits while the RTCCTL. RTCBSY bit = 1. Bit 7 Reserved Seiko Epson Corporation 9-10 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
The day of the week counter is a base-7 counter and the setting/read values are 0x0 to 0x6. Table 9.6.2 lists the correspondence between the count value and day of the week. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 9-11 (Rev. 1.2)
SLEEP mode and SVD stops with the register settings maintained at those before entering SLEEP mode. After the CPU returns to normal mode, CLK_SVD is supplied and the SVD operation resumes. Seiko Epson Corporation 10-2 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
SVDCTL.MODEN bit = 1, wait for at least SVD circuit response time before reading the SVDINTF.SVDDT bit (refer to “Supply Voltage Detector Characteristics, SVD circuit response time t ” in the “Electrical Char- acteristics” chapter). Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 10-3 (Rev. 1.2)
SVDIF bit). An interrupt request is sent to the interrupt controller only when the SVDINTF.SVDIF bit is set while the interrupt is enabled by the SVDINTE.SVDIE bit. For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation 10-4 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the SVD operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of SVD. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 10-5 (Rev. 1.2)
SVD detection voltage V 0x1e High 0x1d ↑ 0x1c 0x02 ↓ 0x01 0x00, 0x1f Use prohibited For more information, refer to “Supply Voltage Detector Characteristics, SVD detection voltage ” in the “Electrical Characteristics” chapter. Seiko Epson Corporation 10-6 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
This bit indicates the low power supply voltage detection interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 10-7 (Rev. 1.2)
• To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 10-8 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
• A clock source and clock division ratio for generating the count clock are selectable. • Repeat mode or one-shot mode is selectable. • Can generate counter underflow interrupts. Figure 11.1.1 shows the configuration of a T16 channel. Table 11.1.1 T16 Channel Configuration of S1C17W12/W13 Item S1C17W12 S1C17W13 Number of channels 3 channels (Ch.0–Ch.2)
(Set reload data (counter preset data)) 5. Set the following bits when using the interrupt: - Write 1 to the T16_nINTF.UFIF bit. (Clear interrupt flag) - Set the T16_nINTE.UFIE bit to 1. (Enable underflow interrupt) Seiko Epson Corporation 11-2 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
At the same time the counter stops, the T16_ nCTL.PRUN bit is cleared automatically. Select this mode to stop the counter after an interrupt has occurred once, such as for checking a specific lapse of time. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 11-3 (Rev. 1.2)
This bit indicates the T16 Ch.n underflow interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 11-6 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
This bit enables T16 Ch.n underflow interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 11-7 (Rev. 1.2)
• Input pin can be pulled up with an internal resistor. • The output pin is configurable as an open-drain output. Figure 12.1.1 shows the UART2 configuration. Table 12.1.1 UART2 Channel Configuration of S1C17W12/W13 Item S1C17W12 S1C17W13 Number of channels 2 channels (Ch.0 and Ch.1)
- UAnCLK.CLKSRC[1:0] bits (Clock source selection) - UAnCLK.CLKDIV[1:0] bits (Clock division ratio selection = Clock frequency setting) The UART2 operating clock should be selected so that the baud rate generator will be configured easily. Seiko Epson Corporation 12-2 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
(UAnMOD.STPB bit = 1). Parity function The parity function is configured using the UAnMOD.PREN and UAnMOD.PRMD bits. Table 12.4.1 Parity Function Setting UAnMOD.PREN bit UAnMOD.PRMD bit Parity function Odd parity Even parity Non parity Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 12-3 (Rev. 1.2)
- Set the interrupt enable bits in the UAnINTE register to 1. * (Enable interrupts) * The initial value of the UAnINTF.TBEIF bit is 1, therefore, an interrupt will occur immediately after the UA- nINTE.TBEIE bit is set to 1. Seiko Epson Corporation 12-4 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Read the UAnINTF.TBEIF bit UAnINTF.TBEIF = 1 ? Write transmit data to the UAnTXD register Transmit data remained? Wait for an interrupt request (UAnINTF.TBEIF = 1) Figure 12.5.2.2 Data Transmission Flowchart Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 12-5 (Rev. 1.2)
Read receive data (1 byte) from the UAnRXD register the UAnRXD register Read receive data (1 byte) from the UAnRXD register Receive data remained? Receive data remained? Figure 12.5.3.2 Data Reception Flowcharts Seiko Epson Corporation 12-6 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
The received data that encountered an error is still transferred to the receive data buffer and the UAnINTF.FEIF bit (framing error interrupt flag) is set to 1 when the data becomes ready to read from the UAnRXD register. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 12-7 (Rev. 1.2)
For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation 12-8 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Note: The UAnMOD register settings can be altered only when the UAnCTL.MODEN bit = 0. UART2 Ch.n Baud–Rate Register Register name Bit name Initial Reset Remarks UAnBR 15–12 – – – 11–8 FMD[3:0] 7–0 BRT[7:0] 0x00 Seiko Epson Corporation 12-10 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Bits 15–8 Reserved Bits 7–0 RXD[7:0] The receive data buffer can be read through these bits. The receive data buffer consists of a 2-byte FIFO, and older received data is read first. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 12-11 (Rev. 1.2)
• Slave mode is capable of being operated in SLEEP mode allowing wake-up by an SPIA interrupt. • Input pins can be pulled up/down with an internal resistor. Figure 13.1.1 shows the SPIA configuration. Table 13.1.1 SPIA Channel Configuration of S1C17W12/W13 Item S1C17W12...
16-bit timer channel and converts it to the SPICLKn. The 16-bit timer must be run with an appro- priate reload data set. The SPICLKn frequency (baud rate) and the 16-bit timer reload data are calculated by the equations shown below. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 13-3 (Rev. 1.2)
1. Assert the slave select signal by controlling the general-purpose output port (if necessary). 2. Check to see if the SPInINTF.TBEIF bit is set to 1 (transmit buffer empty). 3. Write transmit data to the SPInTXD register. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 13-5 (Rev. 1.2)
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SPInTXD register Transmit data remained? Wait for an interrupt request (SPInINTF.TBEIF = 1) Negate the slave select signal output from a general-purpose port Figure 13.5.2.2 Data Transmission Flowchart in Master Mode Seiko Epson Corporation 13-6 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
SPInTXD register data written is completed. If no transmit data is written during this period, the data bits input from the SDIn pin are shifted and output from the SDOn pin without being modified. Seiko Epson Corporation 13-8 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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Data (W) → SPInTXD Data (W) → SPInTXD Software operations SPInRXD → Data (R) SPInRXD → Data (R) Figure 13.5.5.1 Example of Data Transfer Operations in Slave Mode (SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 13-9 (Rev. 1.2)
“Interrupt Controller” chapter. The SPInINTF register also contains the BSY bit that indicates the SPIA operating status. Figure 13.6.1 shows the SPInINTF.BSY and SPInINTF.TENDIF bit set timings. Seiko Epson Corporation 13-10 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Note: The SPInMOD register settings can be altered only when the SPInCTL.MODEN bit = 0. SPIA Ch.n Control Register Register name Bit name Initial Reset Remarks SPInCTL 15–8 – 0x00 – – 7–2 – 0x00 – SFTRST MODEN Bits 15–2 Reserved Seiko Epson Corporation 13-12 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
The following shows the correspondence between the bit and interrupt: SPInINTE.OEIE bit: Overrun error interrupt SPInINTE.TENDIE bit: End-of-transmission interrupt SPInINTE.RBFIE bit: Receive buffer full interrupt SPInINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation 13-14 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
• The internal pull-up resistors for the I/O ports cannot be used for pulling up SDA and SCL. • When the I2C is set into master mode, no other master device can be connected to the I bus. Seiko Epson Corporation 14-2 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
14.3.3.1). Note: The I C bus transfer rate is limited to 100 kbit/s in standard mode or 400 kbit/s in fast mode. Do not set a transfer rate exceeding the limit. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 14-3 (Rev. 1.2)
- Set the I2CnCTL.MST bit to 0. (Set slave mode) - Set the I2CnCTL.SFTRST bit to 1. (Execute software reset) - Set the I2CnCTL.MODEN bit to 1. (Enable I2C Ch.n operations) Seiko Epson Corporation 14-4 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
I2CnINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START condition. When the repeated START condition has been generated, the I2CnINTF.STARTIF and I2CnINTF.TBEIF bits are both set to 1 same as when a START condition has been generated. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 14-5 (Rev. 1.2)
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Last data sent? Retry? Write 1 to the I2CnCTL.TXSTOP bit Write data to the I2CnTXD register Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 14.4.2.2 Master Mode Data Transmission Flowchart Seiko Epson Corporation 14-6 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
This reading triggers the I2C Ch.n to start subsequent data reception. Generating a STOP or repeated START condition It is the same as the data transmission in master mode. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 14-7 (Rev. 1.2)
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Read receive data from the I2CnRXD register Write 1 to the I2CnCTL.TXSTOP bit Write 1 to the I2CnCTL.TXSTOP bit Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 14.4.3.2 Master Mode Data Reception Flowchart Seiko Epson Corporation 14-8 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Clear the I2CnINTF.STARTIF bit by writing 1 after the interrupt has occurred. 9. Write the first address to the I2CnTXD.TXD[7:1] bits and 1 that represents READ as the data transfer direc- tion to the I2CnTXD.TXD0 bit. 10. Perform data reception. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 14-9 (Rev. 1.2)
Go to Step 6 when a STOP condition interrupt has occurred. ii. Go to Step 2 when a START condition interrupt has occurred. 6. Clear the I2CnINTF.STOPIF bit and then terminate data sending operations. Seiko Epson Corporation 14-10 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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A: ACK, A: NACK, Saddr/R: Slave address + R(1), Saddr/W: Slave address + W(0), STARTIF = 1 Data n: 8-bit data Figure 14.4.5.1 Example of Data Sending Operations in Slave Mode Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 14-11 (Rev. 1.2)
I2C Ch.n sends an ACK and pulls down SCL to low. The received data in the shift register is transferred to the receive data buffer and the I2CnINTF.RBFIF and I2CnINTF.BYTEENDIF bits are both set to 1. Af- ter that, the received data can be read out from the I2CnRXD register. Seiko Epson Corporation 14-12 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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Wait for an interrupt request (I2CnINTF.RBFIF = 1) Last data received next? Write 1 to the I2CnCTL.TXNACK bit Read receive data from the I2CnRXD register Last data received? Figure 14.4.6.2 Slave Mode Data Reception Flowchart Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 14-13 (Rev. 1.2)
If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is regarded as an automatic bus clearing failure. In this case, the I2C Ch.n clears the I2CnCTL.TXSTART bit to 0 and sets both the I2CnINTF.ERRIF and I2CnINTF.STARTIF bits to 1. Seiko Epson Corporation 14-14 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
4 <Master mode only> When 1 is written to the I2CnCTL.TX- I2CnINTF.ERRIF = 1 START bit while the I2CnINTF.BSY bit = 0 (Refer to “Automatic Automatic bus clearing I2CnCTL.TXSTART = 0 Bus Clearing Operation.”) failure I2CnINTF.STARTIF = 1 Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 14-15 (Rev. 1.2)
(Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Note: The I2CnCLK register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 14-17 (Rev. 1.2)
The I2CnOADR.OADR[9:0] bits are effective in 10-bit address mode (I2CnMOD.OADR10 bit = 1), or the I2CnOADR.OADR[6:0] bits are effective in 7-bit address mode (I2CnMOD.OADR10 bit = 0). Note: The I2CnOADR register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko Epson Corporation 14-18 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Bit 0 MODEN This bit enables the I2C operations. 1 (R/W): Enable I2C operations (The operating clock is supplied.) 0 (R/W): Disable I2C operations (The operating clock is stopped.) Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 14-19 (Rev. 1.2)
0 (R): SDA = High level Bit 11 SCLLOW This bit indicates that SCL is set to low level. 1 (R): SCL = Low level 0 (R): SCL = High level Seiko Epson Corporation 14-20 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
- The capture circuit captures counter values using external/software trigger signals and generates interrupts. (Can be used to measure external event periods/cycles.) Figure 15.1.1 shows the T16B configuration. Table 15.1.1 T16B Channel Configuration of S1C17W12/W13 Item S1C17W12 S1C17W13 Number of channels 2 channels (Ch.0 and Ch.1)
If the port is shared with the T16B pin and other functions, the T16B input/output function must be assigned to the port before activating T16B. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation 15-2 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Figure 15.3.4.1 Count Timing (During Count Up Operation) Note: When running the counter using the event counter clock, two dummy clocks must be input be- fore the first counting up/down can be performed. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 15-3 (Rev. 1.2)
- T16BnCTL.CNTMD[1:0] bits (Select count up/down operation) - T16BnCTL.ONEST bit (Select one-shot/repeat operation) - Set the T16BnCTL.PRESET bit to 1. (Reset counter) - Set the T16BnCTL.RUN bit to 1. (Start counting) Seiko Epson Corporation 15-4 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
MAX value. If the MAX value is altered to a value smaller than the current counter value, the counter is cleared to 0x0000 and continues counting up to the new MAX value. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 15-5 (Rev. 1.2)
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MODEN = 1 PRESET = 1 RUN = 1 Software operation Data (W) → MC[15:0] RUN = 1 RUN = 0 Hardware operation 0xffff Count cycle MAX value Counter Time 0x0000 Seiko Epson Corporation 15-6 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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Data (W) → MC[15:0] RUN = 1 RUN = 1 0xffff MAX value Counter Time 0x0000 RUN = 0 Figure 15.4.2.3 Operations in Repeat Up/Down Count and One-shot Up/Down Count Modes Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 15-7 (Rev. 1.2)
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If the captured data stored in the T16BnCCRm register is overwritten by the next trigger when the T16BnINTF. CMPCAPmIF bit is still set, an overwrite error occurs (the T16BnINTF.CAPOWmIF bit is set). Seiko Epson Corporation 15-14 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
The TOUT signal polarity (active level) can be set using the T16BnCCCTLm.TOUTINV bit. It is set to active high by setting the T16BnCCCTLm.TOUTINV bit to 0 and active low by setting to 1. Figures 15.4.4.2 and 15.4.4.3 show the TOUT output waveforms. Seiko Epson Corporation 15-16 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16B Ch.n operating clock (counter clock). Bit 3 Reserved Bits 2–0 CLKSRC[2:0] These bits select the clock source of T16B Ch.n. Seiko Epson Corporation 15-22 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
T16BnCTL.ONEST bit setting (see Table 15.6.2). Bit 3 ONEST This bit selects the counter repeat/one-shot mode. The count mode is configured with this selection and the T16BnCTL.CNTMD[1:0] bit settings (see Table 15.6.2). Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 15-23 (Rev. 1.2)
T16BnCTL.MODEN bit to 1 until the T16BnCS.BSY bit is set to 0 from 1. • Do not set the T16BnMC.MC[15:0] bits to 0x0000. T16B Ch.n Timer Counter Data Register Register name Bit name Initial Reset Remarks T16BnTC 15–0 TC[15:0] 0x0000 – Seiko Epson Corporation 15-24 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
This bit indicates the currently set count direction. 1 (R): Count up 0 (R): Count down Bit 0 This bit indicates the counter operating status. 1 (R): Running 0 (R): Idle Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 15-25 (Rev. 1.2)
Note: The configuration of the T16BnINTF.CAPOWmIF and T16BnINTF.CMPCAPmIF bits depends on the model. The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. Seiko Epson Corporation 15-26 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 15-27 (Rev. 1.2)
These bits select the trigger edge(s) of the trigger signal at which the counter value is captured in the T16BnCCRm register in capture mode (see Table 15.6.4). The T16BnCCCTLm.CAPTRG[1:0] bits are control bits for capture mode and are ineffective in comparator mode. Seiko Epson Corporation 15-28 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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The signal becomes inactive by the MATCH signal. All count modes TOUTnm The signal becomes inactive by the MATCHm or MATCHm+1 signal. TOUTnm+1 The signal becomes inactive by the MATCHm+1 or MATCHm signal. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 15-29 (Rev. 1.2)
In capture mode, this register is configured as the capture register and the counter value captured by the capture trigger signal is loaded. Seiko Epson Corporation 15-30 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
IC. The buzzer output duration can also be controlled via software. An output start/stop procedure and the SNDA operations are shown below. Normal buzzer output start/stop procedure 1. Set the SNDSEL.MOSEL[1:0] bits to 0x0. (Set normal buzzer mode) Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 16-3 (Rev. 1.2)
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Buzzer signal frequency [Hz] BZOUT DUTY: Buzzer signal duty ratio [%] However, the following settings are prohibited: • Settings as SNDDAT.SFRQ[7:0] bits ≤ SNDDAT.SLEN[5:0] bits • Settings as SNDDAT.SFRQ[7:0] bits = 0x00 Seiko Epson Corporation 16-4 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
At the same time, the SNDINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SND- INTF.SBSY bit is cleared to 0. Figure 16.4.3.1 shows a buzzer output timing chart in one-shot buzzer mode. Seiko Epson Corporation 16-6 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
At the same time, the SNDINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SNDINTF.SBSY bit is cleared to 0. Figure 16.4.4.1 shows a melody mode operation timing chart. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 16-7 (Rev. 1.2)
This bit sets whether the SNDA operating clock is supplied in DEBUG mode or not. 1 (R/W): Clock supplied in DEBUG mode 0 (R/W): No clock supplied in DEBUG mode Bit 7 Reserved Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 16-9 (Rev. 1.2)
This bit specifies a tie or slur (continuous play with the previous note) in melody mode. 1 (R/W): Enable tie/slur 0 (R/W): Disable tie/slur This bit is ignored in normal buzzer mode/one-shot buzzer mode. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 16-11 (Rev. 1.2)
No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective The following shows the correspondence between the bit and interrupt: SNDINTF.EMIF bit: Sound buffer empty interrupt SNDINTF.EDIF bit: Sound output completion interrupt Seiko Epson Corporation 16-12 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
• Automatic data setting function for continuous data transmission. • Output signal inverting function supporting various formats. • EL lamp drive waveform can be generated for an application example. Figure 17.1.1 shows the REMC2 configuration. Table 17.1.1 REMC2 Channel Configuration of S1C17W12/W13 Item S1C17W12 S1C17W13...
1. Write 1 to the REMDBCTL.REMCRST bit. (Reset REMC2) 2. Configure the REMCLK.CLKSRC[1:0] and REMCLK.CLKDIV[3:0] bits. (Configure operating clock) 3. Assign the REMC2 output function to the port. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation 17-2 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
The REMC2 outputs the logical AND between the carrier signal output from the carrier generator and the data sig- nal output from the data signal generator. Figure 17.4.3.1 shows an example of the output waveform. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 17-3 (Rev. 1.2)
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The data signal is generated by comparing the values of the 16-bit counter for data signal generation (REM- DBCNT.DBCNT[15:0] bits) that runs with CLK_REMC2 and the setting values of the REMAPLEN. APLEN[15:0] and REMDBLEN.DBLEN[15:0] bits. Figure 17.4.3.3 shows an example of the data signal gen- erated. Seiko Epson Corporation 17-4 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
(REMDBCTL.TRMD bit = 1), the counter stops automatically when the counter value is matched with the REMDBLEN.DBLEN[15:0] bit-setting value. 17.4.4 Continuous Data Transmission and Compare Buffers Figure 17.4.4.1 shows an operation example of continuous data transmission with the compare buffer enabled. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 17-5 (Rev. 1.2)
For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation 17-6 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
This bit starts/stops counting by the internal counters (16-bit counter for data signal generation and 8-bit counter for carrier generation). 1 (W): Start counting 0 (W): Stop counting 1 (R): Counting 0 (R): Idle Seiko Epson Corporation 17-8 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
0x0000 H0/S0 Cleared by writing 1 to the REMDBCTL.REMCRST bit. Bits 15–0 DBCNT[15:0] The current value of the 16-bit counter for data signal generation can be read out through these bits. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 17-9 (Rev. 1.2)
This bit indicates whether the value written to the REMAPLEN.APLEN[15:0] bits is transferred to the REMAPLEN buffer or not. (See Figure 17.4.4.1.) 1 (R): Transfer to the REMAPLEN buffer has not completed. 0 (R): Transfer to the REMAPLEN buffer has completed. Seiko Epson Corporation 17-10 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
These bits set the carrier signal cycle. A carrier signal cycle begins with the 8-bit counter for carrier generation = 0x00 and ends when the counter exceeds the REMCARR.CRPER[7:0] bit-setting value. (See Figure 17.4.3.2.) Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 17-11 (Rev. 1.2)
This bit enables carrier modulation. 1 (R/W): Enable carrier modulation 0 (R/W): Disable carrier modulation (output data signal only) Note: When carrier modulation is disabled, the REMDBCTL.REMOINV bit should be set to 0. Seiko Epson Corporation 17-12 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
• The LCD contrast is adjustable into 16 steps. • Includes a power supply for 1/3 bias driving (allows external voltages to be applied). • Can generate interrupts every frame. Figure 18.1.1 shows the LCD4A configuration. Table 18.1.1 LCD4A Configuration of S1C17W12/W13 S1C17W12 S1C17W13 Item...
1. Enable the clock source in the clock generator if it is stopped (refer to “Clock Generator” in the “Power Supply, Reset, and Clocks” chapter). 2. Set the following LCD4CLK register bits: - LCD4CLK.CLKSRC[1:0] bits (Clock source selection) Seiko Epson Corporation 18-2 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
V can be generated by the internal LCD power supply circuit (LCD voltage regu- lator and LCD voltage booster). One or all voltages can also be applied from outside the IC. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 18-3 (Rev. 1.2)
LCD voltage booster on. Figure 18.4.3.1 shows an external connection example for external voltage appli- cation mode 2. LCD4 LCD2 LCD3 Figure 18.4.3.1 External Connection Example for External Voltage Application Mode 2 (when V is applied) Seiko Epson Corporation 18-4 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
8. Write display data to the display data RAM. 9. Set the following bits when using the interrupt: - Write 1 to the LCD4INTF.FRMIF bit. (Clear interrupt flag) - Set the LCD4INTE.FRMIE bit to 1. (Enable LCD4A interrupt) Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 18-5 (Rev. 1.2)
SEG2–19 SEG0–25 COM0–1 Static COM0 Unused common pins output an OFF waveform that turns the segments off. 18.5.5 Drive Waveforms Figures 18.5.5.1 to 18.5.5.4 show drive waveform examples by drive duty. Seiko Epson Corporation 18-6 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
To activate the n-line inverse AC drive function, select the number of lines to be inverted using the LCD4TIM2.NLINE[1:0] bits. The setting value should be determined after being evaluated using the actual circuit board. Note that using the n-line inverse AC drive function increases current consumption. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 18-9 (Rev. 1.2)
When the LCD4DSP.COMREV bit is set to 1, memory bits are assigned to common pins in ascending order. When the LCD4DSP.COMREV bit is set to 0, memory bits are assigned to common pins in descending order. Seiko Epson Corporation 18-10 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the LCD4A operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of the LCD4A. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 18-17 (Rev. 1.2)
These bits set the frame frequency. For more information, refer to “Frame Frequency.” Bits 7–2 Reserved Bits 1–0 LDUTY[1:0] These bits set the drive duty. For more information, refer to “Drive Duty Switching.” Seiko Epson Corporation 18-18 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
For more information, see Figures 18.6.3.1 to 18.6.3.4. Bit 5 COMREV This bit selects the common pin assignment direction. 1 (R/W): Normal assignment 0 (R/W): Inverse assignment For more information, see Figures 18.6.3.1 to 18.6.3.4. Seiko Epson Corporation 18-20 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
• Provides an output and continuous oscillation function for monitoring the oscillation frequency. • Can generate reference oscillation completion, sensor (A and B) oscillation completion, measurement counter overflow error, and time base counter overflow error interrupts. Figure 19.1.1 shows the RFC configuration. Table 19.1.1 RFC Channel Configuration of S1C17W12/W13 S1C17W12 S1C17W13 Item...
(Clear interrupt flags) - Set the interrupt enable bits in the RFCnINTE register to 1. (Enable interrupts) 3. Assign the RFC input/output function to the ports. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 19-3 (Rev. 1.2)
To obtain the difference between the reference oscillation and sensor oscillation clock count values from the measurement counter simply, appropriate initial values must be set to the measurement counter before starting reference oscillation. Seiko Epson Corporation 19-4 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
The measurement counter overflow sets the RFCnINTF.EREFIF bit to 1 indicating that the reference oscil- lation has been terminated normally. If the RFCnINTE.EREFIE bit = 1, a reference oscillation completion interrupt request occurs at this point. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 19-5 (Rev. 1.2)
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Performing reference oscillation and sensor oscillation with the same resistor and capacitor results n ≈ m. The difference between n and m is a conversion error. Table 19.4.4.1 lists the error factors. (n: measurement counter initial value, m: measurement counter value at the end of sensor oscillation) Seiko Epson Corporation 19-6 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 19-7 (Rev. 1.2)
This bit sets the RFCLKOn pin to output the divided-by-two oscillation clock. 1 (R/W): Divided-by-two clock output 0 (R/W): Oscillation clock output For more information, refer to “CR Oscillation Frequency Monitoring Function.” Seiko Epson Corporation 19-8 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
This bit controls CR oscillation for sensor A. This bit also indicates the CR oscillation status. 1 (W): Start oscillation 0 (W): Stop oscillation 1 (R): Being oscillated 0 (R): Stopped Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 19-9 (Rev. 1.2)
Note: The time base counter must be set from the low-order value (RFCnTCL.TC[15:0] bits) first when data is set using a 16-bit access instruction. The counter may not be set to the correct value if the high-order value (RFCnTCH.TC[23:16] bits) is written first. Seiko Epson Corporation 19-10 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
%rs[6:0] is written to the mode setting register. (%rd: not used) ld.cw %rd,%rs imm7[6:0] is written to the mode setting register. (%rd: not used) ld.cw %rd,imm7 Output mode setting value Operation mode setting value Figure 20.2.1 Mode Setting Register Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 20-1 (Rev. 1.2)
*3 The component values should be determined after performing matching evaluation of the resonator mounted on the printed cir- cuit board actually used. *4 R is not required when using the DSIO pin as a general-purpose I/O port. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 21-1 (Rev. 1.2)
Oscillation start time – – µs Oscillation frequency 25 °C 1.6 to 3.6 V IOSC 1.2 to 1.6 V 1.6 to 3.6 V -40 to 85 °C 1.2 to 1.6 V Seiko Epson Corporation 21-4 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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CLGOSC1.OSC1SELCR bit = 1 31.04 32.00 32.96 OSC1I oscillation frequency *1 CLGOSC1.CGI1[2:0] bits = 0x0, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), C = 7 pF) Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 21-5...
1,000 – – times retained for 10 years. *1 Assumed that Erasing + Programming as count of 1. The count includes programming in the factory for shipment with ROM data programmed. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 21-7 (Rev. 1.2)
Input voltage [V] (∗ For over voltage tolerant fail-safe type port) High-level output current characteristic Ta = 85 °C, Max. value –V = 1.2 V = 1.6 V = 3.6 V Seiko Epson Corporation 21-8 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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*1 If CLK_SVD is configured in the neighborhood of 32 kHz, the SVDINTF.SVDDT bit is masked during the t period and it re- SVDEN tains the previous value. CLK_SVD SVDCTL.MODEN 0x1e 0x10 SVDCTL.SVDC[4:0] SVDINTF.SVDDT Invalid Valid Invalid Valid SVDEN Seiko Epson Corporation 21-10 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
*3 The LCD drive voltage is lower than the LCD4PWR.LC[3:0] bit settings when V = 1.2 to 1.6 V. See the LCD drive voltage-supply voltage characteristic graph shown below. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL 21-13 (Rev. 1.2)
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LCD circuit current-load characteristic Ta = 25 °C, Typ. value, LCD4PWR.LC[3:0] bits = 0xf, when a load is connected to the V pin only LCD4PWR.VCSEL bit = 0 LCD4PWR.VCSEL bit= 1 [µA] Seiko Epson Corporation 21-14 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
*4: When OSC3 CR oscillator is selected *5: When OSC3 crystal/ceramic oscillator is selected *6: The following pins are not available in the S1C17W12 SQFN7-48PIN package. , OSC1, OSC2, OSC3, OSC4, SEG0–SEG1, SEG20–SEG25 (18SEG × 4COM) *7: The following pins are not available in the S1C17W13 SQFN7-48PIN package.
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Symbol Name Recommended components X'tal1 32 kHz crystal resonator C-002RX (R = 50 kW (Max.), C = 7 pF) manufactured by Seiko Epson Corporation OSC1 gate capacitor Trimmer capacitor or ceramic capacitor OSC1 drain capacitor Ceramic capacitor X’tal3 Crystal resonator...
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/0.45 Figure 23.2 SQFN7-48PIN Package Dimensions * The potential of the EXPOSED DIE PAD is the same as that of the substrate potential (V ) on the back of the IC. Seiko Epson Corporation 23-2 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
• Using a crystal resonator with lower C value decreases current consumption. However, these configurations may reduce the oscillation margin and increase the frequency error, therefore, be sure to perform matching evaluation using the actual printed circuit board. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL AP-B-1 (Rev. 1.2)
• Setting the LCD voltage regulator into heavy load protection mode (LCD4PWR.HVLD bit = 1) increases current consumption. Heavy load protection mode should be set only when the display becomes unstable. Seiko Epson Corporation AP-B-2 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
± 1 V. The C should be placed as close to the V pin as possible and use a sufficiently thick wiring pattern that allows current of several tens of mA to flow. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL AP-C-1 (Rev. 1.2)
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In this case, C can be omitted by connecting between the V and V pins directly. When these pins are not short-circuited, is required even if super economy mode is not used. Seiko Epson Corporation AP-C-2 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
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(2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL AP-C-3 (Rev. 1.2)
• Execute the resending process via software after executing the receive error handler with a parity check. For details of the pin functions and the function switch control, see the “I/O Ports” chapter. For the UART con- trol and details of receive errors, see the “UART” chapter. Seiko Epson Corporation S1C17W12/W13 TECHNICAL MANUAL AP-D-1 (Rev. 1.2)
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“intXX_handler” can be used for software interrupts. (3) The program code is written in the “.text” section. (4) Sets the stack pointer. (5) Sets the number of Flash memory read cycles. (See the “Memory and Bus” chapter.) Seiko Epson Corporation AP-E-2 S1C17W12/W13 TECHNICAL MANUAL (Rev. 1.2)
REVISION HISTORY Revision History Code No. Page Contents 413520200 New establishment 413520201 6-17, Corrected the PDIOEN register table. AP-A-9 PDOEN[4:3], PDOEN[1:0] → PDOEN[4:0]. 18-2 Corrected Table 18.2.1.1. COM/SEG pins: I/O = O → A Added a note. • When an LCD panel is connected, the LCD4CTL.LCDDIS bit should be set to 1. If it is set to 0, the LCD panel characteristics may fluctuate.