Initial Reset; Initial Reset Circuit; Reset Terminal (Reset) - Epson S1C63003 Technical Manual

4

Initial Reset

4.1

initial Reset Circuit

The S1C63003/004/008/016 should be reset to initialize the internal circuits. There are two ways of doing this.
(1) External initial reset by the RESET terminal
(2) External initial reset by simultaneous high input to P00–P03 ports (mask option)
The circuits are initialized by either (1) or (2). When the power is turned on, be sure to initialize using the reset func-
tion. It is not guaranteed that the circuits are initialized by only turning the power on.
Figure 4.1.1 shows the configuration of the initial reset circuit.
OSC1
OSC1
oscillation
OSC2
circuit
Mask option
P00
P01
P02
P03
RESET
V
SS
4.2

Reset Terminal (ReSeT)

Initial reset can be executed externally by setting the reset terminal to a high level (V
is released by setting the reset terminal to a low level (V
maintained by the RS latch and becomes the internal initial reset signal. The RS latch is designed to be released by
a 16 Hz signal (high) that is divided by the OSC1 clock. Therefore in normal operation, a maximum of 1,024/f
seconds (32 msec when f
OSC1
goes to low level. Be sure to maintain a reset input of 0.1 msec or more. However, when turning the power on, the
reset terminal should be set at a high level as in the timing shown in Figure 4.2.1.
Note that a reset pulse shorter than 100 nsec is rejected as noise.
The reset terminal should be set to 0.9•V
After that, a level of 0.5•V
The reset terminal incorporates a pull-down resistor and a mask option is provided to select whether the resistor is
used or not.
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
1 kHz
16 Hz
Divider
1 Hz
Time
authorize
circuit
Figure 4. 1.1 Configuration of initial reset circuit
= 32.768 kHz) is needed until the internal initial reset is released after the reset terminal
1.1 V
V
DD
RESET
Power on
Figure 4. 2.1 Initial reset at power on
or more (high level) until the supply voltage becomes 1.1 V or more.
DD
or more should be maintained more than 2.0 msec.
DD
Seiko epson Corporation
Mask option
Noise
reject
circuit
R Q
S
) and the CPU starts operating. The reset input signal is
SS
0.9•V or more (high level)
DD
0.5•V
DD
2.0 msec or more
4 iniTial ReSeT
Internal
initial
reset
). After that the initial reset
DD
OSC1
4-1