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20 i
C MaSTeR (i2CM)
The slave device returns ACK (0) to the master if the data is received. If the data is not received, the SDA line is
not pulled down, which the I2CM module interprets to mean a NAK (1) (transmission failed).
SDA0 (output)
SDA0 (input)
SCL0 (output)
The I2CM module includes two status bits for transmission control: TBUSY/I2CM_CTL register and RTACK/
I2CM_DAT register.
The TBUSY flag indicates the data transmission status. This flag becomes 1 when transmission starts (including
slave address transmission) and reverts to 0 once data transmission ends. Inspect the flag to check whether the
I2CM module is currently transmitting or at standby.
The RTACK bit indicates whether or not the slave device returned an ACK for the previous transmission. RT-
ACK is 0 if an ACK was returned and 1 if ACK was not returned.
Data reception control
The procedure for receiving data is described below. When receiving data, the slave address must be sent with
the transfer direction bit set to 1.
To receive data, set RXE/I2CM_DAT register to 1 for receiving 1 byte. When TXE/I2CM_DAT register is set
to 1 for sending the slave address, RXE can also be set to 1 at the same time. If both TXE and RXE are set to 1,
TXE takes priority.
When RXE is set to 1, allowing receiving to start, the I2CM module starts outputting the clock from the SCL0
pin with the SDA line at high impedance. The data is shifted into the shift register from the MSB first in sync
with the clock.
RXE is reset to 0 when D7 is loaded.
The received data is loaded to RTDT[7:0] once the 8-bit data has been received in the shift register.
The I2CM module includes two status bits for receive control: RBRDY/I2CM_DAT register and RBUSY/
I2CM_CTL register.
The RBRDY flag indicates the received data status. This flag becomes 1 when the data received in the shift regis-
ter is loaded to RTDT[7:0] and reverts to 0 when the received data is read out from RTDT[7:0]. Interrupts can also
be generated once the flag value becomes 1.
The RBUSY flag indicates the receiving operation status. This flag is 1 when receiving starts and reverts to 0 when
the data is received. Inspect the flag to determine whether the I2CM module is currently receiving or in standby.
The I2CM module outputs 9 clocks with each data reception. In the 9th clock cycle, an ACK or NAK is sent to
the slave via the SDA0 pin. The bit state sent can be set in RTACK/I2CM_DAT register. To send ACK, set RT-
ACK to 0. To send NAK, set RTACK to 1.
note: To wait for reception using polling in the S1C17602/621, follow the procedures given below using
the RBUSY flag. Interrupts to the CPU are disabled because polling accurately determines the
two state transitions 3 and 4.
1. Disable interrupts to the CPU using the di instruction.
2. Write 1 to RXE to prepare for receiving.
3. Wait for RBUSY to become 1 (reception start).
4. Wait for RBUSY to become 0 (reception end).
5. Read out RTDT (received data).
6. Enables interrupts to the CPU using the ei instruction.
20-4
D7
1
Start condition
Figure 20.
5.3 ACK and NAK
Seiko epson Corporation
D6
D0
2
S1C17624/604/622/602/621 TeChniCal Manual
ACK
NAK
8
9
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