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POR
POR (Power On Reset) issues a reset request when the rise of V
ensure that the system will be reset properly when the power is turned on. Figure 2.2.3.1 shows an example of
POR internal reset operation according to variations in V
V
DD
V
Internal state
For the POR electrical specifications, refer to "POR characteristics" in the "Electrical Characteristics" chapter.
Key-entry reset
Inputting a low level signal of a certain period to the I/O port pins configured to a reset input issues a reset re-
quest. This function must be enabled using an I/O port register. For more information, refer to the "I/O Ports"
chapter.
Watchdog timer reset
Setting the watchdog timer into reset mode will issue a reset request when the counter overflows. This helps re-
turn the runaway CPU to a normal operating state. For more information, refer to the "Watchdog timer" chapter.
Supply voltage detector reset
By enabling the low power supply voltage detection reset function, the supply voltage detector will issue a reset
request when a drop in the power supply voltage is detected. This makes it possible to put the system into reset
state if the IC must be stopped under a low voltage condition. For more information, refer to the "Supply Volt-
age Detector" chapter.
Peripheral circuit software reset
Some peripheral circuits provide a control bit for software reset (MODEN or SFTRST). Setting this bit initial-
izes the peripheral circuit control bits. Note, however, that the software reset operations depend on the periph-
eral circuit. For more information, refer to "Control Registers" in each peripheral circuit chapter.
Note: The MODEN bit of some peripheral circuits does not issue software reset.
2.2.4 Initialization Conditions (Reset Groups)
A different initialization condition is set for the CPU registers and peripheral circuit control bits, individually. The
reset group refers to an initialization condition. Initialization is performed when a reset source included in a reset
group issues a reset request. Table 2.2.4.1 lists the reset groups. For the reset group to initialize the registers and con-
trol bits, refer to the "CPU and Debugger" chapter or "Control Registers" in each peripheral circuit chapter.
Reset group
H0
H1
S0
S1C17W03/W04 TECHNICAL MANUAL
(Rev. 1.2)
SS
X
RST
Indefinite (operating limit)
X
Figure 2.2.3.1 Example of Internal Reset by POR
Table 2.2.4.1 List of Reset Groups
Reset source
#RESET pin
POR
Key-entry reset
Supply voltage detector reset
Watchdog timer reset
#RESET pin
POR
Peripheral circuit software reset
(MODEN and SFTRST bits. The
software reset operations de-
pend on the peripheral circuit.
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
is detected. Reset requests from this circuit
DD
.
DD
RUN
RESET state
RST
RUN
Reset cancelation timing
Reset state is maintained for the reset
hold time t
after the reset request is
RSTR
canceled.
Reset state is canceled immediately
after the reset request is canceled.
CPU RUN state
2-5
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