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2.2.3 Reset Sources
The reset source refers to causes that request system initialization. The following shows the reset sources.
#RESET pin
Inputting a reset signal with a certain low level period to the #RESET pin issues a reset request.
Furthermore, a power-on-reset function can be implemented by connecting an external capacitor to the #RE-
SET pin.
Watchdog timer reset
The watchdog timer issues a reset request when the counter overflows. This helps return the runaway CPU to a
normal operating state. For more information, refer to the "Watchdog timer" chapter.
Supply voltage detector reset
By enabling the low power supply voltage detection reset function, the supply voltage detector will issue a reset
request when a drop in the power supply voltage is detected. This makes it possible to put the system into reset
state if the IC must be stopped under a low voltage condition. For more information, refer to the "Supply Volt-
age Detector" chapter.
Peripheral circuit software reset
Some peripheral circuits provide a control bit for software reset (MODEN or SFTRST). Setting this bit initial-
izes the peripheral circuit control bits. Note, however, that the software reset operations depend on the periph-
eral circuit. For more information, refer to "Control Registers" in each peripheral circuit chapter.
Note: The MODEN bit of some peripheral circuits does not issue software reset.
2.2.4 Initialization Conditions (Reset Groups)
A different initialization condition is set for the CPU registers and peripheral circuit control bits, individually. The
reset group refers to an initialization condition. Initialization is performed when a reset source included in a reset
group issues a reset request. Table 2.2.4.1 lists the reset groups. For the reset group to initialize the registers and con-
trol bits, refer to the "CPU and Debugger" chapter or "Control Registers" in each peripheral circuit chapter.
Reset group
H0
H1
S0
2.3 Clock Generator (CLG)
2.3.1 Overview
CLG is the clock generator that controls the clock sources and manages clock supply to the CPU and the peripheral
circuits. The main features of CLG are outlined below.
• Supports multiple clock sources.
- IOSC oscillator circuit that oscillates with a fast startup and no external parts required
- High-precision and low-power OSC1 oscillator circuit that uses a 32.768 kHz crystal resonator
- EXOSC clock input circuit that allows input of square wave and sine wave clock signals
• The system clock (SYSCLK), which is used as the operating clock for the CPU and bus, and the peripheral cir-
cuit operating clocks can be configured individually by selecting the suitable clock source and division ratio.
• IOSCCLK output from the IOSC oscillator circuit is used as the boot clock for fast booting.
S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
Table 2.2.4.1 List of Reset Groups
Reset source
#RESET pin
Supply voltage detector reset
Watchdog timer reset
#RESET pin
Peripheral circuit software reset
(MODEN and SFTRST bits. The
software reset operations de-
pend on the peripheral circuit.
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
Reset cancelation timing
Reset state is maintained for the reset
hold time t
after the reset request is
RSTR
canceled.
Reset state is canceled immediately
after the reset request is canceled.
2-3
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