Time-Base Timer Mode - Fujitsu MB95630H Series Hardware Manual

MB95630H Series
3.5.4

Time-base Timer Mode

In time-base timer mode, only the main clock oscillator, the subclock oscillator,
the time-base timer, and the watch prescaler operate. The CPU and the
operating clock for peripheral functions are stopped in this mode.
■ Operations in Time-base Timer Mode
The time-base timer mode is a mode in which main clock supply is stopped except the clock
supply to the time-base timer. In this mode, while retaining the contents of registers and RAM
existing at the point immediately before the device transits to time-base timer mode, the device
stops all functions except the time-base timer, external interrupt and low-voltage detection
reset.
Subclock oscillation and sub-CR clock oscillation can be enabled or disabled by the subclock
oscillation enable bit and the sub-CR clock oscillation enable bit in the system clock control
register 2 (SYCC2:SOSCE, SCRE) respectively. If the subclock oscillates, the watch prescaler
continues its operation.
In the case of hardware watchdog timer, if it is enabled in standby mode by the non-volatile
register function, in time-base timer mode, the sub-CR clock does not stop and the hardware
watchdog timer continues its operation. For details, see "CHAPTER 26 NON-VOLATILE
REGISTER (NVR) INTERFACE".
● Transition to time-base timer mode
If the clock mode monitor bits in the system clock control register (SYCC:SCM[2:0]) are
"0b010", "0b110", or "0b111", writing "1" to the watch bit in the standby control register
(STBC:TMD) causes the device to transit to time-base timer mode.
The device can transit to time-base timer mode only when the clock mode is main clock mode,
main CR clock mode or main CR PLL clock mode.
After the device transits to time-base time mode, if the pin state setting bit in the standby
control register (STBC:SPL) is "0", the states of the external pins are kept; if the SPL bit is "1",
the states of the external pins become high impedance (a pin is pulled up if the pull-up resistor
connection for that pin is selected in the pull-up register).
● Release from time-base timer mode
The device is released from time-base timer mode by a reset, a time-base timer interrupt, or an
external interrupt.
Subclock oscillation and sub-CR clock oscillation can be enabled or disabled by setting the
subclock oscillation enable bit (SOSCE) and the sub-CR clock oscillation enable bit (SCRE) in
the system clock control register 2 (SYCC2). When the subclock oscillates, the device can be
released from time-base timer mode by an interrupt from the watch prescaler.
With the deep standby mode control bit (STBC2:DSTBYX) set to "0", even after a reset occurs
or an interrupt is generated by a peripheral function, the device transits to sleep mode until the
Flash recovery wait time elapses.
However, if a program is being executed on the RAM, no Flash recovery wait time occurs.
MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 3 CLOCK CONTROLLER
3.5 Operations in Low Power Consumption
Mode (Standby Mode)
51