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CHAPTER 6 LOW POWER CONSUMPTION MODE
6.5.2
Time-base Timer Mode
Time-base timer mode causes the microcontroller operation to stop with the exception
of the source oscillation and the time-base timer. All functions other than time-base
timer are deactivated.
■ Switching to Time-base Timer Mode
Writing "0" to the TMDX and STP bit of LPMCR triggers a switch to time-base timer mode.
At this time, if the MCS bit of the clock selection register (CKSCR) is "0", the microcontroller enters PLL
time-base timer mode. If the MCS bit of CKSCR is "1", the microcontroller enters main time-base timer
mode.
Note:
Since the STP bit setting overrides the TMDX bit setting when "0" is written to the TMDX and STP
bits at the same time, the mode switches to stop mode.
●
Data retention function
In time-base timer mode, the contents of dedicated registers, such as accumulators and internal RAM, are
retained.
●
Operation during an interrupt request
Writing "0" to the TMDX bit of LPMCR during an interrupt request does not trigger switching to time-base
timer mode.
●
Status of pins
Selection of whether the external pins retain the state they had immediately before switching to time-base
timer mode or go to high-impedance with switching to this mode can be controlled by the SPL bit of
LPMCR.
■ Release of Time-base Timer Mode
The low power consumption control circuit releases time-base timer mode. Release is caused by input of a
reset or an interrupt. If time-base timer mode is released by a reset, the microcontroller is placed in the
reset state after its release from time-base timer mode.
●
Return to normal mode by a reset
If time-base timer mode is released by a reset, the microcontroller is placed in the reset state after release
from time-base timer mode.
●
Return to normal mode by an external reset
Since an external reset does not initialize the MCS bit of the clock selection register (CKSCR) to "1", PLL
clock mode remains selected (MCS of CKSCR = 0) or main clock mode remains selected (MCS of CKSCR =
1). On return from time-base timer mode by an external reset, the CPU starts operation using PLL/Main
clock immediately after time-base timer mode is released.
102
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