Timer Mode Control Register (Mcntm) (M = 0, 1) - NEC V850ES/DJ2 User Manual

7.2.5 Timer Mode Control Register (MCNTm) (m = 0, 1)

MCNTCm is an 8-bit register that controls the operation of the timer counter MCNTm. MCNTCm is set
with an 8-bit memory instruction.
MTRESET ="0" clears MCNTCm to 00H.
Figure 7-6: Timer Mode Control Register (MCNTm) Format (1/2)
7
Note1
MCNTCm CAE
R/W R/W
Notes: 1. CAE is a flag that is only available in MCNTC0.
2. 0 at 0x12
MCNTC
1 at 0x13
MCNTC
Cautions: 1. First of all, set CAE = " 1 " to operate this macro.
2. To enable the operation the PCE bit has to be set to "1", after setting the CAE,
SMC02, SMC01 and SMC00 bits.
3. At DJ2 (6 SM channels): to set this macro into power save mode first set PCE1 = 0
then set the CAE and PCE0 bit simultaneously to "0"
Remark: SMCL02, SMCL01, SMCL00 bit and CAE bit can be written at same time in purpose to
decrease frequency of register access.
CAE
0 Disables the internal clock supply
1 Enables the internal clock supply
By setting CAE = 0 the count operation is stopped. This is used to reduce the power consumption.
Remark: If the CAE bit will be set to "0" the counter MCNTCn register will hold it's value and the PWM
output pin will hold its actual Level. To clear the counter and set the PWM output pin to inac-
tive level, PCEm = 0 has to be set beforehand.
PCEm
Operation is stopped with clearing the timer value
0
and the associated PWM output pins will be set to Low level
1 Operation enable
Remarks: 1. the CAE and PCE0 bit can be set simultaneously to "0" (same register)
2. If only the 4 SM channels of the MCMT0 counter are used the power consumption can
be reduced by writing the CAE bit and the PCE0 bit simultaneously. In other cases set
PCE1 bit = 0 beforehand.
120
Chapter 7 Meter Controller Driver
6 5 4
0 0 PCEm
R R/W R/W
Control of internal clock operation
Timer counter operation control
Preliminary User's Manual U17763EE1V1UD00
3 2 1
0 SMCLm2 SMCLm1 SMCLm0
R R/W R/W
Initial
0 Address
value
Note2
R/W
0