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Symbol
7
6
TMC0
0
0
OVF0
16-bit timer register overflow detection
0
Overflow not detected
1
Overflow detected
TMC03 TMC02 TMC01
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Cautions 1. Switch the clear mode and the TO0 output timing after stopping the timer operation (by
setting TMC01 to TMC03 to 0, 0, 0).
2. The valid edge of the TI0/INTP0 pin is specified by the external interrupt mode register
(INTM0) and the sampling clock frequency is selected by the sampling clock select register
(SCS).
3. When using the PWM mode, set the PWM mode and then set data to CR00.
Remark TO0:
16-bit timer/event counter output pin
TI0:
16-bit timer/event counter input pin
TM0:
16-bit timer register
CR00: Compare register 00
130
CHAPTER 6 16-BIT TIMER/EVENT COUNTER
Figure 6-5. Format of 16-Bit Timer Mode Control Register
5
4
3
0
0
TMC03 TMC02
Operating mode & clear
mode selection
Operation stop
(TM0 cleared to 0)
PWM mode
(free-running)
Free-running mode
Clear & start on TI0 valid
edge
Clear & start on match
between TM0 and CR00
User's Manual U11302EJ4V0UM
2
1
<0>
Address
TMC01
OVF0
FF48H
TO0 output timing
selection
No change
PWM pulse output
Match between TM0 and
CR00
Match between TM0 and
CR00 or TI0 valid edge
Match between TM0 and
CR00
Match between TM0 and
CR00 or TI0 valid edge
Match between TM0 and
CR00
Match between TM0 and
CR00 or TI0 valid edge
After reset
R/W
00H
R/W
Interrupt request
generation
Not generated
Generated on match
between TM0 and CR00
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