Figure 14-1.Error Correction Coprocessor Block Diagram/Programming Model; System Description - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Error Correction Coprocessor (DSP1618/28 Only)

14.1 System Description

A block diagram of the coprocessor and its interface to the DSP1600 core is shown in
EOVF
EREADY
EBUSY
Figure 14-1. Error Correction Coprocessor Block Diagram/Programming Model
The ECCP internal registers are accessed indirectly through the address and data registers (ear and edr). The
control register (ECON) and the traceback length register (TBLR) are used to program the operating mode of the
ECCP. The symbol registers (S0H0—S5H5, ZIG10, and ZQG32), the generating polynomial registers (ZIG10,
ZQG32, and G54), and the channel impulse registers (S0H0—S5H5) are used as input to the ECCP for MLSE or
convolutional decoding. Following a Viterbi decoding operation, the decoded symbol is read out of the decoded
symbol register (DSR). All internal states of these memory-mapped registers are accessible and controllable by
the DSP program. However, during periods of simultaneous DSP core and ECCP activity, ECCP internal registers
and the shared bank RAM4 are not accessible to the user's DSP code.
14-2
(continued)
ear
IDB
edr
eir
CONTROL UNIT
ECON
RAM4
DRAFT COPY
ECCP
BRANCH METRIC
UNIT
SiHi, i = 0, . . . ,5
ZIG10
ZQG32
G54
UPDATE UNIT
NS[63:0]
PS[63:0]
SYC
MIDX
MACH
MACL
TRACEBACK UNIT
TBLR
DSR
TBSR
Information Manual
April 1998
Figure 14-1.
5-4500
Lucent Technologies Inc.