Internal Memories; External Memory Interface (Emi) - Lucent Technologies DSP1617 Information Manual

Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Hardware Architecture

2.3 Internal Memories

All memory (internal and external) is 16 bits wide. The DSP1611 ROM contains 1K words and is preprogrammed
with a variety of boot routines that make it easy for systems to download programs and data to the DSP1611's
large internal RAM space. The DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629 all feature large, mask-
programmable internal ROM memories that can be encoded with programs, fixed data, or both. The DSP1617
ROM contains 24 Kwords, the DSP1618 ROM contains 16 Kwords, the DSP1618x24 ROM contains 24 Kwords,
the DSP1627 ROM contains 36 Kwords, the DSP1627x32 ROM contains 32 Kwords, the DSP1628 contains
48 Kwords, and the DSP1629 contains 48 Kwords. The internal ROM of the code to support the hardware devel-
opment system is included in ROMless devices supplied by Lucent Technologies and should be included in cus-
tomer-created ROM programs.
The internal dual-port RAM contains multiple banks of zero-wait-state memory. Each bank consists of 1K of 16-bit
words and has separate ports to the instruction/coefficient buses and data buses. A program can reference the
memory from either port at any time transparently and without restriction. The DSP1600 core automatically per-
forms the multiplexing. In the event that references to both ports of a single bank are made simultaneously, the
DSP1600 core automatically performs the data port access and then inserts a wait-state followed by the instruc-
tion/coefficient port access.
A program can be downloaded from slow off-chip memory into the dual-port RAM and then executed with-
out wait-states. Dual-port RAM is also useful for improving the performance of convolution in cases where the
coefficients are adaptive. Full-speed, remote, in-circuit emulation is possible because the dual-port RAM can be
downloaded through the JTAG port. This download capability is also useful for self-test.

2.4 External Memory Interface (EMI)

The DSP1611/17/18/27/28/29 provides a 16-bit external address bus (AB[15:0]) and a 16-bit, external, bidirectional
data bus (DB[15:0]). These buses are multiplexed between the internal instruction/coefficient memory buses (X
space) and the data memory buses (Y space). The multiplexing is automatically controlled by the core that deter-
mines the memory space to be accessed from the instruction, the memory map, and the address.
Because only Y space or X space can be accessed at one time through the EMI, a sequencer automatically han-
dles the case when a program calls for simultaneous access of X space and Y space. For example, if a program is
being executed from external ROM and an instruction calls for a read from external RAM, the sequencer first
accesses the X space external ROM and then reads the data from external RAM. One extra instruction cycle is
required, in addition to any external wait-states that are present if external memory is used, compared to internal
operation.
Four external memory enables (ERAMLO, IO, ERAMHI, and EROM) are outputs that control the selection of exter-
1
nal memory segments. One of the IO addresses is individually decoded to provide an enable (DSEL ) for memory-
mapped I/O peripherals.
Each of the five enables can be programmed individually to delay their assertion one-half of a free-running CKO
period from the beginning of the external cycle. This allows a mix of high- and low-speed devices without bus con-
1
flicts or expensive glue logic. The DSEL enable is normally active-low, but it can be programmed to be active-
high. The ERAMLO, ERAMHI, EROM, and IO signals are active-low.
Each of the memory segments can have a different number of wait-states associated with it where a wait-state is
an extra instruction cycle inserted in the read or write cycle to allow for slower memories. The number of wait-
states is programmable from 0 to 15 by setting bits in the mwait register.
1.Not available in the DSP1627/28/29.
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