Figure 11-5.The Simplest Boundary-Scan Register Cell - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
11.3 Elements of the JTAG Test Logic
11.3.4 The Boundary-Scan Register—JBSR (continued)
In the preceding tables, the direction of shifting conforms to the definition of the MSB as the bit being closest to TDI
as given in the standard.
Before dealing with the details of the individual cells, attention should be paid to the common features of the differ-
ent types of boundary-scan cells:

All types of cells load or capture from their parallel inputs in the capture-DR state. In addition, they all contain
parallel output stages into which new data is loaded or updated in the update-DR state.

The MODE signal replaces both of the standard-defined signals Input Mode Control (which selects the source of
input data into the device) and Output Mode Control (which selects the source of output data from the device).
The MODE signal is derived from the instruction decoder and drives all of the cells in the JBSR register. The
MODE signal is equal to one during EXTEST and INTEST and is equal to zero during SAMPLE and in the test-
logic-reset state (i.e., during normal device functions).

The CAPTURE, SHIFT, and UPDATE signals are derived from the TAP Controller and are gated with signals
from the instruction decoder. If the current instruction selects the JBSR (i.e., with instructions EXTEST, INTEST,
and SAMPLE being current), these signals are active. Otherwise, they are all inactive.

SI and SO are the serial input and output of each register cell. The scan path is formed by tying the SO signal of
one cell to the SI of the adjacent cell. The standard allows the cells to be assembled in any order with the MSB
cell's SI tied to the TDI pin and the LSB cell's SO tied to the TDO pin.

The JBSR cell clock is derived from TCK.
In visualizing the boundary-scan register, it is useful to think of each cell as a four-terminal unit with the serial data
flowing vertically and the parallel data flowing horizontally as shown in
stacking such four-terminal units on top of each other.
PARALLEL INPUT
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
(continued)
CAPTURE-DR
SHIFT-DR
UPDATE-DR
MODE
Figure 11-5. The Simplest Boundary-Scan Register Cell
DRAFT COPY
Figure
SERIAL OUTPUT
SERIAL INPUT
JTAG Test Access Port
11-5. The JBSR is then formed by
PARALLEL OUTPUT
5-4206
11-11