Figure 11-2.The Tap Controller State Diagram; Overview Of The Jtag Architecture - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
JTAG Test Access Port

11.1 Overview of the JTAG Architecture

The major subcircuits are as follows:
TAP: For the DSP1611/17/18/27, a four-pin test access port (consisting of input pins—TCK, TMS, and TDI and the
output pin—TDO) provides the standard interface to the test logic. No separate TRST (test logic reset) input pin
exists, but a powerup reset circuit internal to the device resets the TAP Controller to its inactive state if the device is
powered up.
The DSP1628/29 provides a five-pin test access port consisting of the TCK, TMS, TDI, and TDO pins—as in the
DSP1611/17/18/27—plus a TRST (test logic reset input) pin.
TAP Controller: The TAP Controller implements the finite state machine that controls the operation of the test
logic as defined by the standard. The TMS input value sampled on the rising edge of TCK controls the state transi-
tions. The state diagram underlying the TAP Controller is shown in
TEST LOGIC
1
RESET
0
RUN-TEST/
0
IDLE
Note: State transitions are controlled by the value of TMS sampled on the rising edge of TCK.
Instruction Register (JIR): A 4-bit scannable JTAG instruction register with parallel input and parallel output
stages and holds 1 of 16 different instruction codes. The JTAG instructions and their detailed functions are pre-
sented in Section 11.4, The JTAG Instruction
The Instruction Register—JIR.
11-2
(continued)
POWERUP
1
SELECT-
DR-SCAN
1
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
0
EXIT2-DR
UPDATE-DR
1
Figure 11-2. The TAP Controller State Diagram
Set. The physical structure of the JIR is covered in
DRAFT COPY
Figure 11-2.
1
0
0
0
1
1
0
0
1
1
0
Information Manual
April 1998
SELECT-
1
IR-SCAN
0
1
CAPTURE-IR
0
SHIFT-IR 0
1
1
EXIT1-IR
0
PAUSE-IR
0
1
0
EXIT2-IR
1
UPDATE-IR
1 0
Section 11.3.3,
Lucent Technologies Inc.
5-4130