Latent Reads - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
8.2 Programmer Interface

8.2.2 Latent Reads

While in active mode, reading from a logical PIO port is accomplished by an actual read of the single physical port
on the DSP. If a read of the parallel input register (physical port) is performed, a transaction to the external system
is performed on the logical port. Reads from the logical port imply that:

All reads take their data from the on-chip parallel input register.

As data is read from the internal parallel input register, a read transaction to the external system is initiated.

Upon completion of the external read transaction, data received from the external system (logical ports 0
through 7) is loaded into the parallel input register.
Reads from the external system are latent because data is read from the internal parallel input register and then
new data is accepted into the parallel input register from a logical port. For example, to read a string of four words
of data (d0, d1, d2, d3) from the PIO port, the following actions are required:
1. The first instruction reads meaningless data from the parallel input register and initiates the transaction to bring
the first word (d0) from the external device.
2. The second instruction reads the first word (d0) from the parallel input register and initiates the transaction to
bring the second word (d1) from the external device.
3. The third instruction reads the second word (d1) from the parallel input register and initiates the transaction to
bring the third word (d2) from the external device.
4. The fourth instruction reads the third word (d2) from the parallel input register and initiates the transaction to
bring the fourth word (d3) from the external device.
5. The fifth and final instruction reads the fourth word (d3) from the parallel input register and initiates a transaction
that reads another word of data from the external device and overwrites the last word (d3) in the parallel input
register.
To fetch a vector of data of length N requires N + 1 instructions and generates N + 1 read transactions to the exter-
nal system. In order to fetch a single word that is not already present in the parallel input register, two instructions
are required. Because all logical ports map into the same physical port, a fetch from any logical port takes data
from the parallel input register; subsequently, the external access overwrites the contents of the parallel input reg-
ister with the data from the logical port specified in the instruction.
page 8-18 show the hardware and functional timing for latent reads respectively.
The parallel output register is distinct from the parallel input register. Writing to pdx0 through pdx7 does not alter
the contents of the parallel input register.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
(continued)
DRAFT COPY
Parallel I/O (DSP1617 Only)
Figure 8-11, on page 8-18 and Figure 8-12, on
8-17