Figure 8-6.Passive Mode Output Timing - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Parallel I/O (DSP1617 Only)
8.1 PIO Operation
(continued)
8.1.3 Passive Mode (continued)
Passive Mode Output
The external device drives PODS, and the DSP drives the PB.
As mentioned above for any passive mode access to the PIO, an external device must first pull the PSEL2 pin low.
PSEL1 should also be asserted at this time. If the PIO's status is sought, the external device should drive this input
high. If the contents of the pdx[OUT] register are sought, PSEL1 should be driven low. Then, the passive mode
output transaction (shown in
DSP drives the PB. The data remains valid for a short period after PODS is driven high by the external device. No
clock is shown here because the access is asynchronous and timed by the external device.
PSEL2
(CHIP SELECT)
PSEL1
(DATA MODE)
PODS FROM
EXTERNAL DEVICE
PB
FROM DSP
8-8
Figure 8-6) is initiated by an external device asserting PODS. A short period later, the
Figure 8-6. Passive Mode Output Timing
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Information Manual
April 1998
5-4192
Lucent Technologies Inc.