Table 8-3. The Pio Status Register, Pstat; Table 8-4. The Pio Buffer Flags - Lucent Technologies DSP1617 Information Manual

Digital signal processor
Table of Contents

Advertisement

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Parallel I/O (DSP1617 Only)
8.1 PIO Operation
(continued)
8.1.4 Peripheral Mode (Host Interface) (continued)
Polling the PSTAT register (performed by holding PSEL1 high during a passive read) provides PIO status externally
without requiring any extra pins. This register cannot be read or written under program control and is read only
over the PB. Its sole purpose is to be polled by an external device. The DSP itself is completely oblivious to the
fact that PSTAT has been read. The state of pdx[IN], pdx[OUT], and the flags are unaffected and no internal inter-
rupt is generated.
Table 8-3
PSTAT register.

Table 8-3. The PIO Status Register, PSTAT

Bit
Field
Polling the PSTAT register yields the following information:
 LPIDS: If this bit is set, the PIO is configured for active mode input; otherwise, the input is in passive mode.
(There is no need to present the same information about PODS because PSTAT can only be read during a pas-
sive mode output.)
 PIBF: If set, the parallel input buffer (pdx[IN]) is full. This bit has the same value as the pin by the same name.
 POBE: If set, the parallel output buffer (pdx[OUT]) is empty. This bit has the same value as the pin by the same
name.
Whenever PIDS is passive, PIBF is operative even if PODS is active. Likewise, POBE is operative if PODS is pas-
sive regardless of the mode of PIDS. The PSTAT register can be polled if PODS is passive even if PIDS is active.
PSEL0 only indicates the state of the PIO buffers in peripheral mode. If either PIDS or PODS is active, PSEL0 indi-
cates the channel to which a PIO output is directed.

Table 8-4. The PIO Buffer Flags

PODS
Active
Active
Passive
Passive
† Peripheral mode.
8-10
describes the PSTAT register.
7—3
Reserved
Table 8-4
PIDS
Active
Passive
Active
Passive
DRAFT COPY
Figure 8-10
shows the functional timing for polling the
LPIDS
summarizes the behavior of PIBF and POBE.
PIBF
Low
Operative
Low
Operative
Information Manual
April 1998
2
1
PIBF
POBE
Low
Low
Operative
Operative
Lucent Technologies Inc.
0
POBE

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

Dsp1629Dsp1618Dsp1611Dsp1627Dsp1628

Table of Contents