Figure 2-4.Dsp1617 Block Diagram - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
2.1 Device Architecture Overview
2.1.3 Device Architecture (continued)
DB[15:0]
CKI
CKI2
CKO
RSTB
STOP
TRAP
INT[1:0]
IACK
VEC[3:0] OR IOBIT[7:4]
DO2 OR PSEL1
OLD2 OR PODS
OCK2 OR PSEL2
OBE2 OR POBE
SYNC2 OR PSEL0
ICK2 OR PB0
ILD2 OR PIDS
DI2 OR PB1
IBF2 OR PIBF
DOEN2 OR PB2
SADD2 OR PB3
IOBIT[3:0] OR PB[7:4]
† These registers are accessible through external pins only.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
(continued)
AB[15:0] RWN EXM DSEL
ioc
EXTERNAL MEMORY INTERFACE & EMUX
DUAL-PORT
RAM
4K x 16
YAB YDB XDB
DSP1600 CORE
PIO
pioc
†
PSTAT
M
pdx<0—7>(IN)
U
X
pdx<0—7>(OUT)
Figure 2-4. DSP1617 Block Diagram
DRAFT COPY
I/O EROM ERAMHI ERAMLO
ROM
24K x 16
XAB BMU
aa0
aa1
ar0
ar1
ar2
ar3
IDB
SIO2
powerc
sdx2(OUT)
BIO srta2
sbit
tdms2
cbit
sdx2(IN)
sioc2
saddx2
Hardware Architecture
JTAG
BOUNDARY-SCAN
TDO
jtag
TDI
†
JCON
TCK
†
ID
TMS
†
BYPASS
HDS
†
BREAKPOINT
†
TRACE
TIMER
timerc
timer0
SIO1 DI1
ICK1
sdx(OUT)
ILD1
srta
IBF1
DO1
tdms
OCK1
OLD1
sdx(IN)
OBE1
sioc
SYNC1
SADD1
saddx
DOEN1
5-4142.b
2-5