Table 11-3. Jtag Scan Register (Dsp1611, 1617 And 1618 Only) - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
11.3 Elements of the JTAG Test Logic
11.3.4 The Boundary-Scan Register—JBSR (continued)

Table 11-3. JTAG Scan Register (DSP1611, 1617 and 1618 Only)

Note: The direction of shifting is from TDI to cell 105, to cell 104, . . . , to cell 0, and to TDO.
Cell Type
0—15 O AB[15:0] (cell #0 is AB0, etc.)
16 I
17 O
18—21 O EROM, ERAMLO, ERAMHI, IO
22 O
23—29 B
30 DC Controls cells 23—29, 31—39
31—39 B
40 O
41 O
42 I
43 DC
44 DC
45 DC
46 B
47 B
48 B
49 B
50 DC
51 DC
52 O
53 B
54 OE
55 DC
56 DC
57 I
58 B
59 B
60 DC
61 DC
62 B
63 B
64 B SYNC2/PSEL0/PBSEL
65 DC
66 DC
67 DC
68 B
† Shifting a zero into this cell in the mode to scan a zero into the device will disable the processor clocks the same as the STOP pin will.
‡ For descriptions of the pin multiplexing, see
Management, and Section 7.7.1, SIO2
§ Indicates signal is internal and not necessarily observable at pins depending on how the JTAG is set up.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Signal Name/Function
EXM
RWN
DSEL
DB[6:0]
DB[15:7]
OBE1
IBF1
DI1
Controls cell 46
Controls cell 47
Controls cell 48
ILD1
ICK1
OCK1
OLD1
Controls cell 49
Controls cell 53
DO1
SYNC1
Controls cell 52
Controls cell 58
Controls cell 59
†
STOP
SADD1
DOEN1
Controls cell 63
Controls cell 62
‡
OCK2/PSEL2/PCSN
‡
DO2/PSEL1/PSTAT
‡
Controls cell 64
Controls cell 69
Controls cell 68
‡
ILD2/PIDS
Section 10.1.4, BIO Pin
Features.
(continued)
Cell Type
69 B
70 O
71 DC
72 DC
73 O
74 B
75 B
76 B
77 B
78 DC
79 DC
80 DC
81 DC
82 B
83 DC
84 DC
85 B
86 B
87 B
88 B
89 B
90 DC
91 DC
92 B
93 B
94 I
95 DC
96 DC
97 I
98 DC
99 OE
100 O
101 B
102 O
103 OE
104 I
105 I
Multiplexing, Section 9.4, PHIF Pin
DRAFT COPY
JTAG Test Access Port
Signal Name/Function
OLD2/PODS
IBF2/PIBF
Controls cell 75
Controls cell 74
OBE2/POBE
‡
ICK2/PB0
‡
DI2/PB1
DOEN2/PB2
SADD2/PB3
Controls cell 77
Controls cell 76
Controls cell 82
Controls cell 85
IOBIT0/PB4
Controls cell 87
Controls cell 86
IOBIT1/PB5
IOBIT2/PB6
IOBIT3/PB7
VEC3/IOBIT4
VEC2/IOBIT5
Controls cell 88
Controls cell 89
VEC1/IOBIT6
VEC0/IOBIT7
INT1
Controls cell 92
Controls cell 93
INT0
Controls cell 101
Controls cells 0—15,40—41,70,73,100
IACK
TRAP
CKO
Controls cells 17—22,102
RSTB
Clock Generator
Multiplexing, Section 8.2.3, Power
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
§
11-9