Intel Mode, 16-Bit Write; Figure 9-3. Intel Mode, 16-Bit Write - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only)
9.1 PHIF Operation

9.1.2 Intel Mode, 16-Bit Write

The external device drives PCSN, PIDS, PBSEL, and PB.
In the Intel mode, PIDS is the input data strobe and PODS is the output data strobe with respect to the DSP.
Initially, PB is 3-stated. Data is enabled into the DSP if both PCSN (chip select) and PIDS (input data strobe) are
low. The timing of this action is controlled by whichever of the two goes low last. PBSEL (byte-select) is low, so the
data is transferred to the low byte of the pdx0(IN) register. If PIDS is driven high by the external device, the data is
latched by the DSP. The timing of this action is controlled by PIDS or PCSN whichever goes high first. PBSEL can
now be driven high to transfer data to the high byte of pdx0 (IN). The sense of PBSEL can be reversed by pro-
gramming the phifc register. The default state is shown here. The cycle is completed by another strobe from
PCSN and PIDS. After the rising edge of PIDS latches the high byte into the DSP, the PIBF interrupt is generated
and the PIBF output pin goes high.
PCSN
(CHIP SELECT)
PIDS, FROM
EXTERNAL DEVICE
†
PBSEL
PB, FROM
EXTERNAL DEVICE
†
PIBF
† The logic levels of these pins can be inverted by programming the phifc register.
9-4
(continued)
LOW BYTE WRITE

Figure 9-3. Intel Mode, 16-Bit Write

DRAFT COPY
Information Manual
April 1998
HIGH BYTE WRITE
Lucent Technologies Inc.
5-4496