Table 2-5. Two-Cycle Fetch Internal Pipeline - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
2.1 Device Architecture Overview
2.1.5 Internal Instruction Pipeline (continued)
illustrates the internal pipeline for a two-cycle fetch from X-memory space by using the pt register and a
Table 2-5
concurrent compound read/write of the Y-memory space by using the multiply/ALU instruction: Z : y x = *pt++.

Table 2-5. Two-Cycle Fetch Internal Pipeline

Instruction CKO
Cycle Level
1 1
1 0
2 1
2 0
3 1
3 0
4 1
4 0
5 1
The following describes the actions associated with each of the steps shown in bold in
Instruction CKO
Cycle Level
1 1
1 0
2 1
2 0
3 1
3 0
4 1
4 0
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
(continued)
XAB XDB
xaddr instr
1 0
— —
xaddr instr
2 1
— —
ptaddr
instr
2
— —
xaddr coeff
3
— —
xaddr instr
4 3
The program counter (PC) places xaddr
(X space memory).
The program memory is accessed.
The program memory responds by placing instr
The AAU decoder decodes the instruction, and sets up the YAAU to address the RAM
and the XAAU to place the contents of the pt register on the XAB. The control section
recognizes a two-cycle instruction.
The YAAU places yaddr
1r
decodes instr . The contents of the pt register (ptaddr) are placed on the XAB.
1
The decoder directs a RAM read of data
The data, coeff, from the X memory is transferred to the x register. The data
transferred to the RAM from the y register.
The data is transferred from the RAM to the y register. The RAM is written with
1r
data
.
1w
DRAFT COPY
AAU DAU
DECODE DECODE
— instr
instr instr
0
— instr
instr
instr
1
instr
—
instr instr
1
— instr
instr
instr
2
— instr
Process Description
on the address bus XAB to program memory
1
on the instruction data bus (XDB).
1
on the address bus YAB to the RAM. Also, the DAU decoder
to the DAU. The RAM is accessed.
1r
Hardware Architecture
YAB
yaddr
–1 –1
—
–1
yaddr
0 0
—
0
yaddr
1 1r
—
1
yaddr
1 1w
—
1
yaddr
2 2
Table 2-5.
YDB
—
data
–2
—
data
–1
—
data0
data
1w
data
1r
—
is
1w
2-15