Ad = A Shift As - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998

aD = a SHIFT aS

S
(shift value in a by aS bits)
(aD) ← (a ) >> (aS)
S
(aD) ← (a ) << (aS)
S
(aD) ← (a ) >>> (aS)
S
(aD) ← (a ) <<< (aS)
S
These shift operations use the barrel switch in the BMU to perform shifts by a computed number of bits. The 36-bit
value in a is shifted by the number of bits specified by the value in the high half of aS (bits 31—16), and the 36-bit S
result is written to aD. The values in aSl and the aS guard bits are ignored. If the shift value is negative, the direc-
tion of the shift will automatically be reversed; i.e., a right shift will become a left shift of the same type and vice-
versa.
aD = a >> aS
S
aD = a << aS S
aD = a >>> aS
S
aD = a <<< aS S
In the encoding, aS and a must be different accumulators. Flags are set based on the value written into aD. For
left shifts, the LLV flag is set if any significant bits are lost from the value written into aD. For right shifts, the LLV
flag is set if the shift amount is greater than 35 bits. The SHIFT field selects the type of shift to perform:
00 - >>
Bit 15 14
Field 1 1
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
S
performs an arithmetic right shift.
performs an arithmetic left shift.
performs a logical right shift. (This instruction clears the guard bits [bits 35—32] before
shifting.)
performs a logical left shift.
S
01 - >>>
13 12 11 10
1 1 0 D
Words: 1
Cycles: 2
Group: BMU
Addressing: Register
Flags affected: LMI, LEQ, LLV, LMV,
Interruptible: Yes
Cacheable: Yes
Format: 3b
DRAFT COPY
10 - <<
9 8 7 6
S 1 0 0
ODDP, EVENP, MNS1, NMNS1
Instruction Set Summary
11 - <<<
5 4—3 2
0 SHIFT 0
1 0
0 0
B-46