Register Length Definition; Table 3-3. Registers Nonaccessible By Program, Accessible Through Pins; Table 3-4. Register Length Definition - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
3.1 Register View of the DSP1611/17/18/27/28/29
3.1.1 Types of Registers (continued)
Registers not directly observable by the programmer (denoted by upper case), listed alphabetically:

Table 3-3. Registers Nonaccessible by Program, Accessible Through Pins

Name
BREAKPOINT Four instruction breakpoint registers
BYPASS Bypass the boundary-scan register, 1 bit
ID Identification register, 32 bits
ISR Input shift register
JCON JTAG configuration register, 17 bits
OSR Output shift register
PSTAT PHIF/PIO status register
TRACE Program discontinuity trace buffer
Note: The program counter register (PC) is not directly accessible to be read or written by instruction or external pins.

3.1.2 Register Length Definition

The accumulators are 36 bits long, and the y and p registers are 32 bits long. The letter name y (or p) can mean
either the upper 16 bits of y (or p) or all 32 bits of y (or p) depending on the instruction. The table below defines
when the upper 16 bits are meant and when the full 32 bits are meant.

Table 3-4. Register Length Definition

Register
a0, a1, 16-bit, except 36-bit between accumulators and in aD = y
aa0, aa1
p 16-bit, except 32-bit to accumulators in multiply/ALU instruction
y 16-bit, except 32-bit to accumulators in special function instruction 32-bit, except 16-bit in p = x * y
Note: The user must specify h or l in the ALU immediate, e.g., aD = aS<h,l> OP IM16. p or y is sign-extended to 36 bits for operations with
accumulators.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Description
When Used in Transfers
DRAFT COPY
Software Architecture
(continued)
Type Section
address
data
data
data
c & s
data
c & s PHIF/PIO
address
In Functional Operators
36-bit, except 16-bit in aDh = aSh+1
and aD = aS<h, l> OP IM16
32-bit
HDS
JTAG
JTAG
SIO
JTAG
SIO
HDS
3-5