Internal Instruction Pipeline; Figure 2-9.Hardware Block Diagram For Internal Pipeline - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
2.1 Device Architecture Overview
2.1.4 Memory Space and Bank Switching (continued)
The internal dual-port RAM can be accessed in both the Y space and the X space. This RAM is arranged in multi-
ple 1 Kword banks; and as long as the banks accessed are different, simultaneous data and instruction accesses
can be made. If the same bank is accessed from both memory spaces simultaneously, an extra instruction cycle
(one wait-state) is automatically initiated to carry out the transfer. The data transfer is performed first.
It is important to note that the selection of physical memory within a memory space is automatic because it only
depends on choice of address, and no extra time is involved to switch banks except in the case of accessing the
same bank of internal RAM just described.

2.1.5 Internal Instruction Pipeline

The internal pipeline of fetch, decode, and execute is hidden from the user. The latencies involved are automati-
cally controlled without external intervention. The following is provided for information only. The relevant hardware
is shown in Figure 2-9.
X SPACE MEM.
INSTRUCTIONS
XDB
16
CONTROL
DAU
DECODE
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
(continued)
XAB
16
AAU
DECODE
Figure 2-9. Hardware Block Diagram for Internal Pipeline
DRAFT COPY
PC
XAAU
YAB
YAAU
16
Hardware Architecture
DAU
YDB 16
RAM
5-4143
2-13