Do K - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998

do K {

instr1
.
.
(loop-in cache; cache loaded with new contents)
.
instrN
}
Execute the next N instructions K times.
The next N instructions are loaded into the cache concurrent with their execution. They are then executed within
the cache K – 1 more times at (potentially) higher speed.
The iteration count K can be between 1 and 127 inclusive, and the number of instructions (N) must be between
1 and 15 inclusive.
If K is equal to 0, the iteration count is taken from the value in the cloop register that must contain a value between
1 and 127 inclusive. The cloop register will be decremented to zero at the end of the do instruction.
Notes on cache performance:
The do instruction executes in one cycle. When the cache is used to repeat a block of N instructions, the cycle
timing of the instructions are as follows:
1. The first pass does not affect cycle timing except for the last instruction in the block of N instructions. This
instruction executes in two cycles.
2. During pass 2 through pass K – 1, each instruction is executed in the cache.
3. During the last (Kth) pass, the block of instructions executes inside the cache except for the last instruction
that executes outside the cache.
The instructions remain in the cache memory and may be re-executed using the redo instruction without the
need to reload the cache.
Bit 15 14
Field
0 1
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
13 12 11
1 1 0
Words: 1
Cycles: 1
Group: Cache
Addressing: Immediate
Flags affected: None
Interruptible: No
Cacheable: No
Format: 10
DRAFT COPY
10—7
N
Instruction Set Summary
6—0
K
B-6