Pll Control Signals - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Software Architecture
3.5 Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only)

3.5.1 PLL Control Signals

The input to the PLL comes from the input clock CKI. The PLL cannot operate without this external input clock.
To use the PLL, the PLL must first be allowed to stabilize and lock to the programmed frequency. After the PLL has
locked, the LOCK flag is set and the lock detect circuitry is disabled. The synthesizer can then be selected and
used as the clock source. Setting the PLLSEL bit in the pllc register will switch sources from f
glitching. It is important to note that the setting of the pllc register must be maintained and should not be changed
unless the PLL is deselected as the clock source. Every time the pllc register is written, the LOCK flag is reset.
The LOCK flag is not accessible through any register; its status is tested by the conditional control instruction
if LOCK. (See Section 4.5.1, Control
The frequency of the PLL output clock (f
5-bit M divider. If the PLL is selected and locked, the frequency of the initial processor clock is related to the fre-
quency of CKI by the following equations:
f = f
VCO CKI
f
INTERNAL CLOCK
The frequency of the VCO (f
Note: f
must be at least twice f
VCO
The coding of the Mbits and Nbits is described as follows:
Mbits=M-2
if (N==1)
Nbits=0x7
else
Nbits=N-2
where N ranges from 1 to 8 and M ranges from 2 to 20.
Program the loop filter bits (LF[3:0]) according to
Two other bits in the pllc register (PLLEN and PLLSEL) provide control functions of the PLL. Clearing the PLLEN
bit powers down the PLL. Setting the PLLEN bit powers up the PLL. Clearing the PLLSEL bit deselects the PLL
causing the DSP to be clocked by the 1X CKI input. The PLL can be deselected and powered down in the same
instruction by clearing bits PLLEN and PLLSEL of the pllc register; all remaining pllc bits must remain unchanged.
Setting the PLLSEL bit selects the PLL-generated clock for the source of the DSP internal processor clock. The
pllc register is cleared on reset and powerup; therefore, the DSP comes out of reset with the PLL deselected and
powered down. M and N should be changed only if the PLL is deselected.
The PLL provides a user flag (LOCK) to indicate if the loop has locked. If this flag is not asserted, the PLL output is
unstable. The DSP should not be switched to the PLL-based clock without first checking that the LOCK flag is set.
The LOCK flag is cleared by writing to the pllc register. If the PLL is deselected, it is necessary to wait for the PLL
to relock before the DSP can be switched to the PLL-based clock. Before the input clock (CKI) is stopped, the PLL
should be powered down. Otherwise, the LOCK flag is not reset, and there might be no way to determine if the
PLL is stable when the input clock is applied again.
The lock-in time depends on the operating frequency and the values programmed for M and N (see
3-48
Instructions.)
) is determined by the values loaded into the 3-bit N divider and the
VCO
* M/N
= f = f /2
CKO VCO
) must fall within the range defined in the data sheet.
VCO
.
CKI
Table
DRAFT COPY
(continued)
3-27.
Information Manual
April 1998
to f /2 without
CKI VCO
Table 3-27).
Lucent Technologies Inc.