Clock Synthesis (Dsp1627, Dsp1628, And Dsp1629 Only); Figure 3-19.Clock Source Block Diagram - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998

3.5 Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only)

The DSP1627/28/29 provides an on-chip programmable clock synthesizer that can be driven by an external clock
at a fraction of the desired instruction rate.
output of the synthesizer, or a slow internal ring oscillator can be used as the source for the internal DSP clock.
The clock synthesizer is based on a phase-lock loop (PLL). The terms clock synthesizer and PLL are used inter-
changeably.
On powerup, CKI is used as the clock source for the DSP. This clock is used to generate the internal processor
clocks and CKO. Setting the appropriate bits in the pllc control register (see
thesizer to become the clock source. The powerc register, which is discussed in
Register Bits, can be programmed to override the clock selection, to stop clocks, or to force the use of the slow ring
oscillator clock for low-power operation.
CKI INPUT CLOCK
f
CKI
÷N
Nbits[2:0]
PLL/SYNTHESIZER
Notes:
Signals shown in bold are control bits from the pllc register or the powerc register.
If PLLSEL = 0, DSP runs from the 1X version of CKI input clock.
Other signals from the powerc register also control the clock source.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Figure 3-19
RING
OSCILLATOR
LOCK
(FLAG TO INDICATE LOCK
CONDITION OF PLL)
PHASE
CHARGE
DETECTOR
PUMP
÷M
Mbits[4:0]
Figure 3-19. Clock Source Block Diagram
DRAFT COPY
is the clock source diagram. The 1X CKI input clock, the
Table
SLOWCKI
powerc
VCO CLOCK
f
VCO
VCO
LOOP
FILTER
LF[3:0]
Software Architecture
3-26) will enable the clock syn-
Section 3.6.1, powerc Control
INTERNAL
f
SLOW CLOCK
PROCESSOR
CLOCK
M
f
CKI
U
f
INTERNAL CLOCK
X
÷2
PLLSEL
PLLEN
pllc
3-47