Table 5-5. Replacement Table For Cache Instruction Encoding - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Core Architecture
5.4 Cache and Control
5.4.1 Cache (continued)
The instructions controlling the cache are given below:
do K {
instruction 1
instruction 2
instruction N
}
redo K

Table 5-5. Replacement Table for Cache Instruction Encoding

Bit 15—11
Field T
Replace Value
†
K cloop
1 to 127
N 1 to 15
T 01110
† The assembly-language statements do cloop and redo cloop are used to specify that the number of iterations is to be
taken from the cloop register. K is 0 in the instruction encoding to select cloop.
If the cache is used to execute a block of instructions, the cycle timing of the instructions is as follows:

In the first pass, the instructions are fetched from program memory and the cycle times are the normal out of
cache values except the last instruction in the block of N instructions. This instruction executes in two cycles.

During pass 2 through pass K – 1, each instruction is fetched from cache and the in-cache timing applies.

During the last (Kth) pass, the block of instructions is fetched from cache and the in-cache timing applies except
the timing of the last instruction is the same as if it were out of cache.

If any of the instructions access external memory, programmed wait-states must be added to the cycle counts.
The number of iterations (K) for a do or redo can be set at run time by first moving the number of iterations into the
cloop register (7 bits unsigned) and then issuing the do cloop or redo cloop instruction. The cloop register will
also store the K value if initiated from a do K (K = 1 to 127) instruction and will decrement at each cache loop. At
the completion of the loops, the value of cloop is decremented to 0; hence, cloop needs to be written before each
do cloop or redo cloop.
Cache loops cannot be interrupted. Instructions that cannot be used in the cache are the control group instructions
and any instructions that contain an immediate value as the second word of a two-word instruction.
5-18
(continued)
|
|
Take the number of times the instructions are to be executed from
bits 0 through 6 of the cloop register.
Number of times the instructions are to be executed, encoded in
instruction.
1 to 15 instructions can be included.
DRAFT COPY
10—7
N
Meaning
—
Information Manual
April 1998
6—0
K
Lucent Technologies Inc.