The Jtag Test Access Port; Overview Of The Jtag Architecture; Figure 11-1.The Jtag Block Diagram - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998

11 The JTAG Test Access Port

The DSP1611, DSP1617, DSP1618, and DSP1627 have a standard four-pin test access port known as JTAG.
The DSP1628, and DSP1629 have a five-pin test access port; the standard four-pin JTAG test access port plus an
additional TRST pin. The test port fully conforms to the standards defined in IEEE P1149.1
mandatory features of the standard, the JTAG block of the DSP has most of the optional and recommended fea-
tures of the standard. The JTAG block also has custom test data registers and instructions that, with other features
of the device, provide powerful added functions. These are downloading of test programs through the JTAG port
(for self-test purposes) and on-chip support of the hardware development system (on-chip emulation). The full
description of the custom features is beyond the scope of this manual.
An overview of the JTAG architecture follows in
tions. A more detailed treatment of the material in
ments of the JTAG Test Logic, and

11.1 Overview of the JTAG Architecture

TAP
†
TRST
TDI
TMS
TCK
TDO
TCK
TMS
TRST †
POWERUP RESET
† Only available on the DSP1628/29.
1.The JTAG port of the DSP has successfully passed the IEEE P1149.1 protocol certification test sequence generated by TAPDANCE ® , which
is a rigorous, implementation independent test package developed and administered by Lucent Technologies.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Section
Section 11.1
Section 11.4, The JTAG Instruction
TEST DATA
REGISTERS
TDI
DR
CONTROLS
TDI
IR CONTROLS
Figure 11-1. The JTAG Block Diagram
DRAFT COPY
11.1. Section 11.2 is a brief overview of the JTAG instruc-
and Section 11.2
Set, respectively.
jtag
JCON
JBPR
JIDR
JBSR
INSTRUCTION DECODER
JIR
JSTATUS
1
. In addition to the
is found in Section 11.3, Ele-
JTAG
OUTPUT
STAGE
(JOUT)
TDO
11-1