Control; Table 3-23. Interrupt Control (Inc) Register (Dsp1618/28); Table 3-24. Interrupt Status (Ins) Register (Dsp1618/28); Table 5-6. Control And Status Descriptions - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
5.4 Cache and Control

5.4.2 Control

The control block provides overall DSP1611/17/18/27/28/29 system coordination and is mostly invisible to the
user. Inputs (instructions) are provided to the control block over the program data bus (XDB). The instructions are
decoded by hardware in the control block. Execution of the phases of an instruction is controlled by hardware
throughout the device. The hardware sequences instructions through the pipeline and controls the I/O, the pro-
cessing, the memory accesses, and the timing necessary to perform each operation. A three-level pipeline (fetch
an instruction, decode the instruction, and execute the instruction) is hidden from the user.
Control and status registers in the control section are the inc, ins, alf, and mwait registers (inc, ins, and alf are
described in Tables 5-9 through 5-11). For further information, refer to the sections listed in

Table 5-6. Control and Status Descriptions

Register Section
ins, inc 3.4
alf 4.4
3.2
3.4.6
mwait 6.2

Table 5-7. Interrupt Control (inc) Register (DSP1611/17/27/29)

Bit
15 14—11
Field JINT Reserved OBE2 IBF2 TIMEOUT Reserved INT[1:0] PIDS/PIBF

Table 5-8. Interrupt Status (ins) Register (DSP1611/17/27/29)

Bit 15 14—11
Field JINT Reserved OBE2 IBF2 TIMEOUT Reserved INT[1:0] PIDS/PIBF
Table 5-9. Interrupt Control (inc) Register (DSP1618/28)
Bit
15 14 13
Field JINT rsrvd EOVF EREADY rsrvd OBE2 IBF2 TIMEOUT rsrvd INT[1:0] PIBF POBE OBE IBF
Table 5-10. Interrupt Status (ins) Register (DSP1618/28)
Bit 15 14 13
Field JINT rsrvd EOVF EREADY rsrvd OBE2 IBF2 TIMEOUT rsrvd INT[1:0] PIBF POBE OBE IBF
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
(continued)
Subject
Interrupts
Processor Flags
Memory Space and Addressing
Powerdown with the AWAIT State
Programmable Features
10 9 8
10 9 8
12 11 10
12 11 10
DRAFT COPY
7—6 5—4
7—6 5—4
9 8 7—6
9 8 7—6
Core Architecture
Table 5-6.
3 2
PODS/POBE OBE IBF
3 2
PODS/POBE OBE IBF
5—4 3 2
5—4 3 2
1 0
1 0
1 0
1 0
5-19