Timing; Figure 12-2.Timing Examples - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998

12.4 Timing

Figure 12-2 shows the timing sequence for a short interval. The maximum interval for a DSP with a 33 ns instruc-
tions cycle is:
33 ns
(TCKO,
period of CKO)
CKO
TCLK
TIMER
INTERRUPT
TIMER COUNT
XAB, XDB
FETCH
TIMERC ON
XAB, XDB
The timing example in Figure 12-2
two would give the minimum delay (a starting count of zero would not generate an interrupt). In the example,
timer0 = 2 loads the initial count of two into the counter. The inc register is loaded with a one in bit 8 that enables
the interrupt. Moving 0x30 (00110000) into timerc starts the counting and enables the repeat mode. In the simu-
lation that generated this timing diagram, nops were the other instructions. The use of other instructions will pro-
duce variations in the time delay of one or two instruction cycles because of different instruction timings.
The sequence shows first an instruction that writes a new value to timerc. Time slot 2 is if this instruction appears
on the instruction data bus (XDB).
Five instruction cycles (CKO) later, the first count occurs when the counter decrements to one. At time slot 9, it
decrements to zero and the interrupt is issued. Assuming that an interruptible instruction is currently being exe-
cuted, the interrupt will be serviced with the delay shown (see the interrupt service routine starting in time 13 in
ure 12-2). Meanwhile, back at the timer, the initial value of two has been transferred from the period register into
the counter and the count resumes. At time slot 15, another interrupt is issued that will be ignored in this case. The
same interrupt source is already being serviced and the interrupt routine will not have completed. If an interrupt is
being serviced and the same interrupt is pending next, the interrupt must remain asserted into the next rising edge
of IACK. (See Section 3.4.4, Interrupt
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
65,536
(PRESCALE
value)
1 2 3 4 5 6
2 2 2 2 2 2
timer0 = 2
inc = 0x100
timerc = 0x30
nops executing
Figure 12-2. Timing Examples
shows nearly the minimum delay possible. A starting count of one instead of
Operation.)
DRAFT COPY
65,536 – 1 =
(Max. count in
timer0)
7 8 9 10 11 12 13
1 1 0 0 2 2
FETCH FIRST
WORD OF
INTERRUPT
HANDLER
142 seconds
(Max. delay)
14 15 16 17
1 1 0 0 2 2
Timer
2
5-4211
Fig-
12-5