Instruction Set; Table 4-3. Flags (Conditional Mnemonics) - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR

Instruction Set

4.4 Processor Flags
Table 4-3 shows the complete set of flags that can be used in conditional instructions and their meanings. The
state of the four internal flags (defined above) that causes the condition to be true is enclosed in parentheses after
the description. For example, if testing the condition le, the result is true if either the logical minus (LMI) or logical
equal (LEQ) flags are true.
Availability of flags: The BIO and four of the BMU flags (oddp, evenp, nmns1, and mns1) can be read from the alf
register. The LMI, LEQ, LLV, and LMV can be read from the psw register.

Table 4-3. Flags (Conditional Mnemonics)

Test
pl Result is nonnegative (not LMI) (≥ 0).
eq Result is equal to 0 (LEQ) (= 0).
gt Result is greater than 0 (not LMI and
not LEQ) (> 0).
lvs Logical overflow set (LLV).
mvs Mathematical overflow set (LMV).
†
c0ge Counter 0 greater than or equal to 0.
†
c1ge Counter 1 greater than or equal to 0.
‡
heads Pseudorandom sequence bit set.
true The condition is always satisfied in an if
instruction.
§
allt All true—all BIO input bits tested com-
pared successfully.
§
somet Some true—some BIO input bits tested
compared successfully.
oddp Odd parity from BMU operation.
mns1 Minus 1 result of BMU operation.
npint Not PINT used by hardware develop-
ment system.
††
lock The PLL has achieved lock and is sta-
ble.
† Testing each of these conditions increments the respective counter being tested.
‡ The heads or tails condition is determined by a randomly set or cleared bit respectively. The bit is randomly set with probability of
0.5. The random bit is generated by a 10-stage pseudorandom sequence generator (PSG) that is updated after either a heads or
tails test. The pseudorandom sequence can be reset by writing any value to the pi register except during an interrupt service rou-
tine. While in an interrupt service routine, writing to the pi register will update the register and not reset the PSG. If not in an inter-
rupt service routine, writing to the pi register will reset the PSG. (The pi register will be updated but will be written with the
contents of the PC on the next instruction.) Interrupts must be disabled when writing to the pi register. If an interrupt is taken
after the pi write—before pi is updated with the PC value, the ireturn instruction will not return to the correct location. If the RAND
bit in the auc register is set, however, writing the pi register will never reset the PSG. A random rounding function can be imple-
mented with either heads or tails. (For further information, see
§ These flags are only set after an appropriate write to the BIO port (cbit register).
†† DSP1627/28/29 only.
‡‡ DSP1618/28 only.
4-10
(continued)
Meaning
DRAFT COPY
Test
mi Result is negative (LMI) (< 0).
ne Result is not equal to 0 (not LEQ) (≠ 0).
le Result is less than or equal to 0 (LMI or
LEQ) (≤ 0).
lvc Logical overflow clear (not LLV).
mvc Mathematical overflow clear (not LMV).
†
c0lt Counter 0 less than 0.
†
c1lt Counter 1 less than 0.
‡
tails Pseudorandom sequence bit clear.
false The condition is never satisfied in an if
instruction.
§
allf All false—no BIO input bits tested com-
pared successfully.
§
somef Some false—some BIO input bits tested
did not compare successfully.
evenp Even parity from BMU operation.
nmns1 Not minus 1 result of BMU operation.
njint Not JINT used by hardware develop-
ment system.
‡‡
ebusy ECCP busy indicates error correction
coprocessor activity.
Section 5.1.6, DAU Pseudorandom Sequence Generator
Information Manual
April 1998
Meaning
(PSG).)
Lucent Technologies Inc.