Power Management; Powerc Control Register Bits - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Software Architecture April 1998

3.6 Power Management

There are three different control mechanisms for putting the DSP1611/17/18/27/28/29 into low-power modes: the
powerc control register, the STOP pin, and the AWAIT bit in the alf register. See the appropriate device's data
sheet for the typical power consumption in each mode.

3.6.1 powerc Control Register Bits

The powerc register has 9 bits that power down various portions of the chip and select the clock source. The
encoding for the powerc register is in Tables 3-28, 3-29, 3-30, and 3-31. The bits are described as follows:
XTLOFF: Assertion of the XTLOFF bit powers down the crystal oscillator or the small-signal input circuit disabling
the internal processor clock. Assertion of the XTLOFF bit also disables the crystal oscillator if it is used as a nonin-
verting input buffer. Because the oscillator and the small-signal input circuits take many cycles to stabilize, care
must be taken with the turn-on sequence as described in Section 3.6.5, Power Management Sequencing.
SLOWCKI: Assertion of the SLOWCKI bit selects the ring oscillator as the clock source for the internal clock
instead of CKI (or the clock synthesizer on the DSP1627/28/29). If CKI (or the clock synthesizer) is selected, the
ring oscillator is powered down. Switching of the clocks is synchronized so that no partial or short clock pulses
occur. Two nops should follow the instruction that sets or clears SLOWCKI.
NOCK: Assertion of the NOCK bit synchronously turns off the internal processor clock whether its source is pro-
vided by CKI, the clock synthesizer, or the ring oscillator. The NOCK bit can be cleared by either resetting the chip
with the RSTB pin or by asserting the INT0 or INT1 pins. Two nops should follow the instruction that sets NOCK.
INT0EN: This bit allows the INT0 pin to asynchronously clear the NOCK bit, thereby, allowing the device to con-
tinue program execution from where it left off without any loss of state. No chip reset is required. It is recom-
mended that, if INT0EN is to be used, the INT0 interrupt be disabled in the inc register so that an unintended
interrupt does not occur. After the program resumes, the INT0 interrupt in the ins register should be cleared.
INT1EN: This bit enables the INT1 pin to be used as the NOCK clear exactly like INT0EN previously described.
The following control bits power down the peripheral I/O units of the DSP and can be used to further reduce the
power consumption during standard sleep mode.
SIO1DIS: This is a powerdown signal to the SIO1 I/O unit. It disables the clock input to the unit, thus eliminating
any sleep power associated with the SIO1. Because the gating of the clocks might result in incomplete transac-
tions, it is recommended that this option be used in applications where the SIO1 is not used or if reset might be
used to reenable the SIO1 unit. Otherwise, the first transaction after reenabling the unit might be corrupted.
SIO2DIS: This bit powers down the SIO2 in the same way SIO1DIS powers down the SIO1.
PIODIS (DSP1617 only): This is a powerdown signal to the PIO I/O unit. It disables the clock input to the unit
eliminating any sleep power associated with the PIO. Because the gating of the clocks can result in incomplete
transactions, it is recommended that this option be used in applications where the PIO is not used or if reset can be
used to reenable the PIO unit. Otherwise, the first transaction after reenabling the unit might be corrupted. If the
DSP16A-compatible interrupts are being used, the PIO must remain powered up because the pioc register is
needed.
PHIFDIS (DSP1611/18/27/28/29 only): This is a powerdown signal to the PHIF I/O unit. It disables the clock input
to the unit eliminating any sleep power associated with the PIO. Because the gating of the clocks can result in
incomplete transactions, it is recommended that this option be used in applications where the PHIF is not used or if
reset might be used to reenable the PHIF unit. Otherwise, the first transaction after reenabling the unit might be
corrupted.
TIMERDIS: This is a timer disable signal that disables the clock input to the timer unit. Its function is identical to
the DISABLE field of the timerc control register. Writing a 0 to the TIMERDIS field continues the timer operation.
DRAFT COPY
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