Table 11-4. Jtag Scan Register (Dsp1627/28/29 Only) - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
JTAG Test Access Port
11.3 Elements of the JTAG Test Logic
11.3.4 The Boundary-Scan Register—JBSR (continued)

Table 11-4. JTAG Scan Register (DSP1627/28/29 Only)

Note: The direction of shifting is from TDI to cell 104, to cell 103, . . . , to cell 0, and to TDO.
Cell Type
0 OE
1 O
2 I
3 DC
4 B
5 I
6 O
7 I
8 OE Controls cells 6, 10—25, 49, 50, 78, 79
9 I
10—25 O
26 I
27 O
28—31 O EROM, ERAMLO, ERAMHI, IO
32—36 B
37 DC Controls cells 32—36, 38—48
38—48 B
49 O
50 O
51 I
52 DC
53 B
54 DC
55 B
56 DC
57 B
58 DC
59 B
60 OE
61 O
62 DC
63 B
64 DC
65 B
66 DC
67 B
68 DC
† Please refer to pin multiplexing in
for a description of pin multiplexing of BIO, PHIF, VEC[3:0], and SIO2.
‡ Shifting a zero into this cell in the mode to scan a zero into the device will disable the processor clocks the same as the STOP pin will.
§ Indicates signal is internal and not necessarily observable at pins depending on how the JTAG is set up. If the JTAG SAMPLE instruction is
used, this cell will have a logic one regardless of the state of the pin.
11-10
(continued)
Signal Name/Function
Controls cells 1, 27—31
CKO
RSTB
Controls cell 4
TRAP
‡
STOP
IACK
INT0
INT1
AB[15:0]
EXM
RWN
DB[4:0]
DB[15:5]
OBE1
IBF1
DI1
Controls cell 53
ILD1
Controls cell 55
ICK1
Controls cell 57
OCK1
Controls cell 59
OLD1
Controls cell 61
DO1
Controls cell 63
SYNC1
Controls cell 65
SADD1
Controls cell 67
DOEN1
Controls cell 69
Section 9.4, PHIF Pin Multiplexing,
DRAFT COPY
Cell Type
69 B
70 DC
71 B
72 DC
73 B
74 DC
75 B
76 DC
77 B
78 O
79 O
80 DC
81 B
82 DC
83 B
84 DC
85 B
86 DC
87 B
88 DC
89 B
90 DC
91 B
92 DC
93 B
94 DC
95 B
96 DC
97 B
98 DC
99 B
100 DC
101 B
102 DC
103 B
104 I
Section 10.1.4, BIO Pin Multiplexing, and
Information Manual
April 1998
Signal Name/Function
†
OCK2/PCSN
Controls cell 71
†
DO2/PSTAT
Controls cell 73
†
SYNC2/PDSEL
Controls cell 75
†
ILD2/PIDS
Controls cell 77
†
OLD2/PODS
†
IBF2/PIBF
†
OBE2/POBE
Controls cell 81
†
ICK2/PB0
Controls cell 83
†
DI2/PB1
Controls cell 85
†
DOEN2/PB2
Controls cell 87
†
SADD2/PB3
Controls cell 89
†
IOBIT0/PB4
Controls cell 91
†
IOBIT1/PB5
Controls cell 93
†
IOBIT2/PB6
Controls cell 95
†
IOBIT3/PB7
Controls cell 97
†
VEC3/IOBIT4
Controls cell 99
†
VEC2/IOBIT5
Controls cell 101
†
VEC1/IOBIT6
Controls cell 103
†
VEC0/IOBIT7
§
Clock Generator
Section 7.7.1, SIO2 Features,
Lucent Technologies Inc.