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Lucent Technologies DSP1617 manual available for free PDF download: Information Manual
Lucent Technologies DSP1617 Information Manual (443 pages)
Digital Signal Processor
Brand:
Lucent Technologies
| Category:
Computer Hardware
| Size: 4.55 MB
Table of Contents
Dsp1611/17/18/27/28/29 Digital Signal Processor
4
Table of Contents
4
Introduction
18
General Description
21
Architecture
21
Instruction Set
22
Typical Applications
22
Application Support
23
Hardware Development System
23
Support Software Library
23
Figure 1-1.In-Circuit Emulation with the Flashdsp 1600-JCS
24
Manual Organization
25
Applicable Documentation
26
Hardware Architecture
27
Device Architecture Overview
29
Figure 2-1.Harvard Architecture
29
Harvard Architecture
29
Concurrent Operations
30
Figure 2-2.Concurrent Operations in the DSP1611/17/18/27/28/29
30
Table 2-1. Pipeline Flow for Concurrent Operations
31
Figure 2-3.DSP1611 Block Diagram
32
Figure 2-4.DSP1617 Block Diagram
33
Figure 2-5.DSP1618 Block Diagram
34
Figure 2-6.DSP1627 Block Diagram
35
Figure 2-7.DSP1628 Block Diagram
36
Figure 2-8.DSP1629 Block Diagram
37
Device Architecture
38
Table 2-2. Symbols Used in the Block Diagrams
38
Memory Space and Bank Switching
40
Table 2-3. Memory Space
40
Figure 2-9.Hardware Block Diagram for Internal Pipeline
41
Internal Instruction Pipeline
41
Table 2-4. Single-Cycle Instruction Internal Pipeline
42
Table 2-5. Two-Cycle Fetch Internal Pipeline
43
Core Architecture Overview
44
Data Arithmetic Unit
44
Figure 2-10.DSP1600 Core Functions
44
Y Space Address Arithmetic Unit (YAAU)
45
Cache
46
Control
46
Space Address Arithmetic Unit (XAAU)
46
Internal Memories
47
External Memory Interface (EMI)
47
Bit Manipulation Unit (BMU)
48
Serial Input/Output (SIO) Units
48
Parallel Input/Output (PIO) (DSP1617 Only)
49
Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only)
49
Bit Input/Output (BIO)
50
Jtag
50
Timer
50
Hardware Development System (HDS) Module
51
Clock Synthesis (DSP1627/28/29 Only)
51
Power Management
51
Software Architecture
52
Software Architecture
53
Register View of the DSP1611/17/18/27/28/29
54
Types of Registers
54
Table 3-1. Program-Accessible Registers by Function
54
Table 3-2. Program-Accessible Registers by Type, Listed Alphabetically
55
Figure 3-1.Program-Accessible Registers, DSP1611/17/18/27/28/29
57
Register Length Definition
58
Table 3-3. Registers Nonaccessible by Program, Accessible through Pins
58
Table 3-4. Register Length Definition
58
Register Reset Values
59
Table 3-5. Register Reset Values
59
Flags
60
Table 3-6. Flag Definitions
60
Memory Space and Addressing
61
Y-Memory Space
61
Figure 3-2.Data (Y) Memory Space
61
Table 3-7. Data Memory Map (Y-Memory Space)
62
X-Memory Space
63
Figure 3-3.Instruction/Coefficient (X) Memory Space
63
Table 3-8. DSP1611 Instruction/Coefficient Memory Map (X-Memory Space)
64
Table 3-9. DSP1617 Instruction/Coefficient Memory Map (X-Memory Space)
65
Table 3-10. DSP1618 Instruction/Coefficient Memory Map (X-Memory Space)
65
Table 3-11. Dsp1618X24 Instruction/Coefficient Memory Map (X-Memory Space)
66
Table 3-12. DSP1627 Instruction/Coefficient Memory Map (X-Memory Space)
67
Table 3-13. Dsp1627X32 Instruction/Coefficient Memory Map (X-Memory Space)
68
Table 3-14. Dsp1628X08 Instruction/Coefficient Memory Map (X-Memory Space)
69
Table 3-15. Dsp1628X16 Instruction/Coefficient Memory Map (X-Memory Space)
70
Table 3-16. Dsp1629X10 Instruction/Coefficient Memory Map (X-Memory Space)
71
Table 3-17. Dsp1629X16 Instruction/Coefficient Memory Map (X-Memory Space)
72
Table 3-18. Interrupts in X-Memory Space
73
Arithmetic and Precision
74
Table 3-19. Arithmetic Unit Control (Auc) Register
75
Interrupts
80
Introduction
80
Figure 3-8.Interrupt Operation
81
Interrupt Sources
82
Figure 3-9.DSP16A-Compatible Interrupts (DSP1617 Only)
83
Outputs of Interrupts
84
Table 3-20. Vector Table
84
Interrupt Operation
85
Figure 3-10.Timing Diagram of a Simple Interrupt
86
Figure 3-11.Interrupt Disable Latency
88
Figure 3-12.Interrupt Request Circuit Diagram
89
Figure 3-13.Timing Diagram of Concurrent Interrupts
90
Trap Description
91
Chapter 3 . Software Architecture
91
Software Architecture
91
Figure 3-14.Timing Diagram of User Trap
92
Powerdown with the AWAIT State
93
Figure 3-15.Timing Diagram of Entering and Exiting Powerdown Mode
93
Interrupts in DSP16A-Compatible Mode (DSP1617 Only)
95
Timing Examples, DSP16A-Compatible Mode (DSP1617 Only)
97
Figure 3-16.Timing Sequence of Concurrent Internal and External Interrupts, DSP16A-Compatible Mode
97
Figure 3-17.Timing Sequences of Concurrent Internal and External Interrupts, DSP16A Compatible Mode
98
Figure 3-18.Timing Sequence of Concurrent External Interrupts, DSP16A Compatible Mode
99
Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only)
100
Figure 3-19.Clock Source Block Diagram
100
PLL Control Signals
101
PLL Programming Examples
103
Latency
103
Table 3-25. Latency Times for Switching between CKI and PLL-Based Clocks
103
Table 3-26. Phase-Locked Loop Control (Pllc) Register
104
Table 3-27. PLL Electrical Specifications and Pllc Register Settings
104
Power Management
105
Powerc Control Register Bits
105
Table 3-28. Powerc Fields (DSP1617)
106
Table 3-29. Powerc Fields (DSP1611, DSP1627, and DSP1629)
106
Table 3-30. Powerc Fields (DSP1618 and DSP1628)
106
Table 3-31. Powerc Control Register Fields Description
106
Figure 3-20.Power Management Using the Powerc Register (DSP1611/17/18 Only)
107
Figure 3-21.Power Management Using the Powerc Register (DSP1627/28/29 Only)
108
STOP Pin
109
The Pllc Register Bits (DSP1627/28/29 Only)
109
AWAIT Bit of the Alf Register
109
Power Management Sequencing
110
Power Management Examples
111
Instruction Set
116
Chapter 4 Instruction Set
117
Instruction Cycle Timing
119
Notation
119
Addressing Modes
120
Register Indirect Addressing
120
Compound Addressing
122
Table 4-1. Compound Addressing Instructions
122
Figure 4-1.Compound Addressing
123
Direct Data Addressing
124
Table 4-2. Direct Data Addressing
124
Figure 4-2.Direct Data Addressing
125
Processor Flags
126
Instruction Set
127
Table 4-3. Flags (Conditional Mnemonics)
127
Control Instructions
129
Table 4-4. Control Instructions
129
Table 4-5. Replacement Table for Control Function Instructions
129
Cache Instructions
131
Table 4-6. Example of Execution of Cache Instruction
131
Table 4-7. Replacement Table for Cache Instructions
131
Data Move Instructions
132
Table 4-8. Data Move Instruction Summary
132
Table 4-9. Replacement Table for Data Move Instructions
133
Special Function Group
136
Table 4-10. Special Function Statements
137
Table 4-11. Replacement Table for Special Function Instructions
137
Multiply/Alu Group
139
Table 4-12. Multiply/Alu Instructions
140
Table 4-13. Replacement Table for Multiply/Alu Instructions
141
Table 4-14. Instruction for Loading the X and y Registers into the Squaring Mode
142
Figure 4-3.Compound Addressing with Accumulators or y Register
145
F3 ALU Instructions
146
Table 4-15. F3 ALU Instructions
146
Table 4-16. Replacement Table for ALU Instructions
146
BMU Instructions
147
Table 4-17. Replacement Table for BMU Instructions
147
Figure 4-4.BMU Shifting Operations
148
Figure 4-5.Extraction
149
Figure 4-6.Case 1. Source as and Destination Accumulators Different
150
Figure 4-7.Case 2. Source as and Ad Destination Accumulators the same
150
Figure 4-8.Shuffle Instruction
151
Assembler Ambiguities
152
Table 4-18. Summary of Ambiguous DSP1600 Commands Requiring a Mnemonic
153
Core Architecture
154
Chapter 5 Core Architecture
155
Core Architecture
156
Data Arithmetic Unit
156
Figure 5-1.DAU-Data Arithmetic Unit
156
Alu
157
Inputs and Outputs
157
Multiplier Functions
157
Accumulators
158
Counters
159
Figure 5-2.Conditional Instructions Using Counter Conditionals
159
Table 5-1. Counter Conditionals
159
Figure 5-3.The Ifc con F2 Instruction
161
Table 5-2. C0-C2 Register Functions
161
DAU Pseudorandom Sequence Generator (PSG)
162
Figure 5-4.DAU Pseudorandom Sequence Generator
163
Control Registers
164
Table 5-3. Arithmetic Unit Control (Auc) Register
164
Control Registers
165
Table 5-4. Processor Status Word (Psw) Register
165
Address Arithmetic Unit (XAAU)
166
Inputs and Outputs
166
X-Memory Space Segment Selection
166
Figure 5-5.XAAU-X Address Arithmetic Unit
166
Register Descriptions
167
Y Address Arithmetic Unit (YAAU)
167
Inputs and Outputs
168
Figure 5-6.YAAU-Y Address Arithmetic Unit
168
Y Address Arithmetic Unit (YAAU)
168
Y-Memory Space
169
Register Descriptions
169
Addressing Modes
169
Figure 5-7.Direct Data Addressing
170
Figure 5-8.Use of the Rb and Re Registers
171
Cache and Control
172
Cache
172
Table 5-5. Replacement Table for Cache Instruction Encoding
173
Control
174
Table 3-23. Interrupt Control (Inc) Register (DSP1618/28)
174
Table 3-24. Interrupt Status (Ins) Register (DSP1618/28)
174
Table 5-6. Control and Status Descriptions
174
Table 5-7. Interrupt Control (Inc) Register (DSP1611/17/27/29)
174
Table 5-8. Interrupt Status (Ins) Register (DSP1611/17/27/29)
174
Table 5-11. Alf Register
175
External Memory Interface
176
Chapter 6 External Memory Interface
177
Figure 6-1.External Memory Interface
177
External Memory Interface
178
EMI Function
178
EMI Function
179
Table 6-1. DSP1611 Instruction/Coefficient Memory Map (X-Memory Space)
180
Table 6-2. DSP1617 Instruction/Coefficient Memory Map (X-Memory Space)
181
Table 6-3. DSP1618 Instruction/Coefficient Memory Map (X-Memory Space)
181
Table 6-4. Dsp1618X24 Instruction/Coefficient Memory Map (X-Memory Space)
182
Table 6-5. DSP1627 Instruction/Coefficient Memory Map (X-Memory Space)
183
Table 6-6. Dsp1627X32 Instruction/Coefficient Memory Map (X-Memory Space)
184
Table 6-7. Dsp1628X08 Instruction/Coefficient Memory Map (X-Memory Space)
185
Table 6-8. Dsp1628X16 Instruction/Coefficient Memory Map (X-Memory Space)
186
Table 6-9. Dsp1629X10 Instruction/Coefficient Memory Map (X-Memory Space)
187
Table 6-10. Dsp1629X16 Instruction/Coefficient Memory Map (X-Memory Space)
188
Table 6-11. Data Memory Map (Y-Memory Space)
189
Programmable Features
190
Table 6-12. Mwait Register
190
Table 6-13. Ioc Register
190
Figure 6-2.EMI Example
191
Functional Timing
191
Table 6-14. CKO Options
191
Timing Action with Wait-States
192
Timing Action with Wait-States
193
Timing Examples
194
CKO Timing
194
Write, Read, Read, W = 0
194
Read, Write, Write, W = 0
194
Figure 6-3.CKO Timing
194
Table 6-15. Index of Timing Examples
194
Read, Write, W = 0, Compound Address
194
Read W = 1, Read W = 2
194
Write W = 1
194
Read, Write, W = 0, Compound Address
197
Read W = 1, Read W = 2
198
Figure 6-7.Read, Read
198
Write W = 1
199
Read, Read with Delayed Enable
200
Figure 6-9.Read, Read, with Delayed Enable
200
Write, Read, with Delayed Enable
201
Figure 6-10.Write, Read, with Delayed Enable, no Hold Time
201
Boot-Up from External ROM
202
Figure 6-11.External ROM Boot-Up
202
Memory Sequencer
203
Downloading Code into External Program Memory
205
Table 6-16. Data Memory Map (DSP1617 Only)
205
Serial I/O
208
Chapter 7 Serial I\/O
209
Figure 7-1.Serial I/O Internal Data Path
210
Serial I/O
210
SIO Operation
211
Active Clock Generator
211
Figure 7-2.SIO Clocks
211
Figure 7-3.SIO Active Mode Clock Timing
212
User-Controlled Features
218
Table 7-1. Serial I/O Control (Sioc) Register (DSP1611, DSP1617, and DSP1618 Only)
218
Table 7-2. Serial I/O Control (Sioc) Register (DSP1627/28/29 Only)
218
Table 7-3. Sioc Register Field Definitions
218
The Sioc Register
218
Loopback Control
220
Power Management
220
Serial I/O Pin Descriptions
221
Table 7-4. DSP1611/17/18/27/28/29 Serial I/O Pins
221
Codec Interface
222
Figure 7-9.DSP1611/17/18/27/28/29 to Lucent Technologies CSP1027 Codec Interface
222
Figure 7-10.DSP1611/17/18/27/28/29 to Lucent Technologies T7525 Codec Interface
222
Serial I/O Programming Example
223
Program Segment
223
Multiprocessor Mode Description
224
Figure 7-11.Multiprocessor Connections
224
Multiprocessor Mode Overview
224
Figure 7-12.Destination Address Communication
225
Figure 7-13.Protocol Channel Communication
225
Multiprocessor Mode Overview
225
Detailed Multiprocessor Mode Description
226
Figure 7-14.DSP1611/17/18/27/28/29 Multiprocessor Connections
226
Detailed Multiprocessor Mode Description
227
Figure 7-15.Multiprocessor Mode Time Slots
227
Figure 7-16.Multiprocessor Mode Output Timing
228
Table 7-5. Time-Division Multiplex Slot (Tdms) Register
229
Table 7-6. Serial Receive/Transmit Address (Srta) Register
230
Figure 7-17.DSP1611/17/18/27/28/29 Multiprocessor Communications
232
Suggested Multiprocessor Configuration
233
Multiprocessor Mode Initialization
234
Serial Interface #2
235
Figure 7-18.SIO2-PIO/PHIF Multiplexing
235
SIO2 Features
235
Instructions Using the SIO2
236
Programmable Features
236
Table 7-8. Sioc2 Register (DSP1611, DSP1617, and DSP1618 Only)
236
Table 7-9. Sioc2 Register (DSP1627/28/29 Only)
236
Active Clock Generator
212
Figure 7-4.SIO Passive Mode Input Timing, 16-Bit Words
213
Input Section
213
Figure 7-5.SIO Active Mode Input Timing, 16-Bit Words
214
Figure 7-6.SIO Passive Mode Output Timing, 16-Bit Words
215
Output Section
215
Figure 7-7.SIO Active Mode Output Timing, 16-Bit Words
216
Figure 7-8.SIO Passive Mode Output Timing, 8-Bit Words
217
Parallel I/O (DSP1617 Only)
237
Chapter 8 Parallel I\/O (Dsp1617 Only)
238
Figure 8-1.Parallel I/O Unit
239
Parallel I/O (DSP1617 Only)
239
PIO Operation
240
Active Mode
240
Table 8-1. PIO Strobe Widths
240
Figure 8-2.Active Mode Input Timing (Minimum Width PIDS)
241
Programmer Interface
252
Table 8-5. Port Encoding Pdx<0-7
252
Table 8-6. PIO Control (Pioc) Register
253
Pioc Register Settings
254
Latent Reads
255
Figure 8-11.PIO Latent Reads Hardware
256
Figure 8-12.PIO Latent Reads Timing
256
Power Management
257
Interrupts and the PIO
257
PIO Signals
259
PIO Pin Multiplexing
260
PIO Loopback Test Mode
260
Table 8-7. PIO Signals
260
Table 8-8. PIO Pin Multiplexing
260
Active Mode
241
Figure 8-3.Active Mode Output Timing (Minimum Width PODS)
242
Figure 8-4.PIO Interaccess Timing
243
PIO Interaccess Timing
243
Passive Mode
244
Peripheral Mode (Host Interface)
244
Table 8-2. Function of the PSEL Pins
244
Figure 8-5.Passive Mode Input Timing
245
Figure 8-6.Passive Mode Output Timing
246
Figure 8-7.The DSP as a Microprocessor Peripheral
247
Table 8-3. the PIO Status Register, PSTAT
248
Table 8-4. the PIO Buffer Flags
248
Figure 8-8.Peripheral Mode Input Timing
249
Figure 8-9.Peripheral Output Mode Timing
250
Figure 8-10.Polling PSTAT Timing
251
Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only)
261
Chapter 9 Parallel Host Interface (Phif) (Dsp1611/18/27/28/29 Only)
262
Figure 9-1.Parallel Host Interface
262
Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only)
263
PHIF Operation
264
Intel Mode, 16-Bit Read
265
Figure 9-2. Intel Mode, 16-Bit Read
265
Intel Mode, 16-Bit Write
266
Figure 9-3. Intel Mode, 16-Bit Write
266
Motorola Mode, 16-Bit Read
267
Figure 9-4. Motorola Mode, 16-Bit Read
267
Motorola Mode, 16-Bit Write
268
Figure 9-5. Motorola Mode, 16-Bit Write
268
8-Bit Transfers
269
Accessing the PSTAT Register
269
Table 9-1. the PHIF Status Register, PSTAT
269
Programmer Interface
270
Phifc Register Settings
270
Table 9-2. Parallel Host Interface Control (Phifc) Register
270
Table 9-3. Phifc Register PHIF Function (8-Bit and 16-Bit Modes)
271
Power Management
272
Interrupts and the PHIF
272
PHIF Pin Multiplexing
273
Table 9-4. PHIF Pin Multiplexing of Active Signals
273
Figure 9-6.Overall PHIF Read Cycle
274
Overall Functional Timing
274
Chapter 10 Bit I\/O Unit
276
BIO Hardware Function
277
Bit I/O Unit
277
BIO Configured as Inputs
278
BIO Configured as Outputs
278
Figure 10-2.BIO Configured as Inputs
278
Figure 10-1.BIO Block Diagram
277
BIO Hardware Function
278
Figure 10-3.BIO Configured as Outputs
279
Pin Descriptions
279
BIO Pin Multiplexing
280
Figure 10-4.Logic Flow Diagram for BIO Configuration
280
Software View
280
Table 10-1. BIO Pin Multiplexing
280
Registers
281
Table 10-2. Sbit Register Encoding
281
Table 10-3. Cbit Register Encoding
281
Flags
282
Instructions
282
Examples
282
Table 10-4. Alf Flags
282
Chapter 11 Jtag Test Access Port
285
The JTAG Test Access Port
286
Overview of the JTAG Architecture
286
Figure 11-1.The JTAG Block Diagram
286
Figure 11-2.The TAP Controller State Diagram
287
Overview of the JTAG Architecture
287
Overview of the JTAG Instructions
288
Table 11-1. DSP1611/17/18/27/28/29 JTAG Instructions
288
Elements of the JTAG Test Logic
289
The Test Access Port (TAP)
289
The TAP Controller
290
Figure 11-3.Timing Diagram Example
291
The Instruction Register-JIR
292
Figure 11-4.The JTAG Instruction Register/Decoder Structure
292
The Boundary-Scan Register-JBSR
293
Table 11-2. Boundary-Scan Register Cell Type Definitions
293
Table 11-3. JTAG Scan Register (DSP1611, 1617 and 1618 Only)
294
Table 11-4. JTAG Scan Register (DSP1627/28/29 Only)
295
Figure 11-5.The Simplest Boundary-Scan Register Cell
296
Figure 11-6.Cell Interconnections for a 3-State Pin
298
Figure 11-7.Bidirectional Cell
299
Figure 11-8.Cell Interconnections for a Bidirectional Pin
300
The Bypass Register-JBPR
301
The Device Identification Register-JIDR
301
Figure 11-9.The Device Identification Register, JIDR
301
Table 11-5. JIDR Field Descriptions DSP1617/18/27/28/29
302
Table 11-6. JIDR Field Descriptions DSP1611
303
The JTAG Data Register-Jtag
304
The JTAG Control Register-JCON
304
The JTAG Output Stage-JOUT
304
The JTAG Instruction Set
304
The EXTEST Instruction
304
The INTEST Instruction
304
The SAMPLE Instruction
305
The BYPASS Instruction
305
The IDCODE Instruction
305
Timer
306
Chapter 12 Timer
307
Figure 12-1.Timer Block Diagram
308
Hardware View
308
Programmable Features and Operation
309
Timerc Register Encoding
309
Table 12-1. Timerc Register
309
Timer
309
Timer0 Register
310
The Inc Register
310
Initialization Conditions
310
Program Example
311
Figure 12-2.Timing Examples
312
Timing
312
Chapter 13 Bit Manipulation Unit
314
Bit Manipulation Unit (BMU)
315
Hardware View
315
Figure 13-1.BMU Block Diagram
315
Software View
316
Figure 13-2.Logical Right Shift
316
Instruction Set
316
Shifting Operations
316
Figure 13-3.Left Shifts
317
Figure 13-4.Arithmetic Right Shift
317
Bit Manipulation Unit (BMU)
317
Shifting Operations
317
Software View
317
Normalization
318
Extraction
319
Figure 13-5.Extraction
319
Figure 13-6.Insertion, Case 1. Source and Destination Accumulators Different
320
Insertion
320
Figure 13-7.Insertion, Case 2. Source and Destination Accumulators Are the same
321
Figure 13-8.Shuffle Accumulators
322
Shuffle Accumulators
322
Instruction Encoding
323
Table 13-1. Format 3B: BMU Operations
323
Software Example
324
Chapter 14 Error Correction Coprocessor (Dsp1618/28 Only)
326
Error Correction Coprocessor (DSP1618/28 Only)
327
System Description
327
Figure 14-1.Error Correction Coprocessor Block Diagram/Programming Model
328
System Description
328
Hardware Architecture
329
Branch Metric Unit
329
Update Unit
330
Traceback Unit
330
Table 14-1. Incremental Branch Metrics
330
Interrupts and Flags
331
Traceback RAM
331
DSP Decoding Operation Sequence
332
Figure 14-2.DSP Core Operation Sequence
332
Figure 14-3.ECCP Operation Sequence
333
Operation of the ECCP
333
Software Architecture
334
R-Field Registers
334
Figure 14-4.Register Block Diagram
334
Table 14-2. ECCP Instruction Encoding
335
Table 14-3. Reset State of ECCP Registers
335
ECCP Internal Memory-Mapped Registers
336
Table 14-4. Memory-Mapped Registers
336
Table 14-5. Control Fields of the Control Register
338
ECCP Interrupts and Flags
343
Traceback RAM
343
ECCP Instruction Timing
345
Reseteccp Instruction
345
Updatemlse Instruction with Soft Decision
345
Table 14-6. Representative Updatemlse Instruction Cycles (SH = 0)
346
Updatemlse Instruction with Hard Decision
347
Table 14-7. Representative Updatemlse Instruction Cycles (SH = 1)
347
Updateconv Instruction with Soft Decisions
348
Table 14-8. Representative Updateconv Instruction Cycles (SH = 0)
348
Updateconv Instruction with Hard Decision
349
Traceback Instruction
349
Table 14-9. Representative Updateconv Instruction Cycles (SH = 1)
349
Interface Guide
350
Pin Information
352
Table 15-1. DSP1611/17/18 Pin Descriptions (See Footnotes for any DSP1611/18 Differences.)
352
Table 15-2. DSP1627/28/29 Pin Descriptions
354
Signal Descriptions
356
System Interface
356
External Memory Interface
357
Serial Interface #1
358
PIO/PHIF or Serial Interface #2 and Control I/O Interface
360
Control I/O Interface
362
JTAG Test Interface
362
Resetting DSP161X and DSP162X Devices
363
Powerup Reset
363
Using the TAP to Reset the TAP Controller
363
RSTB Pin Reset
364
Mask-Programmable Options
365
Input Clock Options
365
ROM Security Options (DSP1617/18/27/28/29 Only)
365
Table 15-3. DSP1617/18/27/28/29 ROM Options
365
Table 15-4. DSP1611 Input Clock Options
365
Additional Electrical Characteristics and Requirements for Crystal
366
A Instruction Encoding
369
Instruction Encoding Formats
371
Table A-2. B Field
372
Table A-3. BMU Encodings
372
Field Descriptions
373
Table A-4. con Field
373
Table A-5. D Field
373
Table A-6. DR Field
373
Table A-7. F1 Field
374
Table A-8. F2 Field
374
Table A-10. I Field
375
Table A-9. F3 Field
375
Table A-11. R Field for DSP1617
376
Table A-12. R Field for DSP1611/18/27/28/29
376
Table A-13. S Field
377
Table A-14. si Field
377
Table A-15. SRC2 Field
377
Table A-16. T-Field
377
Table A-17. X Field
378
Table A-18. y Field
378
Table A-19. Z Field
378
Appendix B
380
Appendix B. Instruction Set Summary
382
B Instruction Set Summary
382
Goto JA
382
Goto B
383
If con Goto/Call/Return
384
Table B-1. con Field Encoding
384
Call JA
385
Icall
386
Do K
387
Redo K
388
R = Im16
389
Table B-2. R Field Replacement Values
389
Sr = Im9
391
R = As[L
392
At[L] = R
393
R = y
394
Y = R
395
Z : R
396
Dr = *(Offset
397
(Offset) = Dr
398
If con F2
399
Ifc con F2
400
F1 y
401
F1 y = A0[L
403
F1 y = A1[L
403
F1 y = A0[L
404
F1 y = A1[L
404
F1 X = y
405
F1 X = y
406
F1 Y[L] = y
407
F1 Y[L] = y
408
F1 y = y X = *Pt++[I
409
F1 y = y X = *Pt++[I
410
F1 y = A0 X = *Pt++[I
411
F1 y = A1 X = *Pt++[I
411
F1 y = A0 X = *Pt++[I
412
F1 y = A1 X = *Pt++[I
412
F1 At[L] = y
413
F1 At[L] = y
414
F1 y = Y[L
415
F1 y = Y[L
416
F1 Z : Y[L
417
F1 Z : Y[L
418
F1 Z : At[L
419
F1 Z : At[L
420
F1 Z : y X = *Pt++[I
421
F1 Z : y X = *Pt++[I
422
Ad = as OP at
423
Ad = as OP P
424
Ad = As<H,L> OP IM16
425
Ad = a SHIFT as
427
Ad = as SHIFT Arm
428
Ad = as SHIFT IM16
429
Ad = Exp (as
430
Ad = Norm (As, Arm
431
Ad = Extracts (As, Arm
432
Ad = Extractz (As, Arm
432
Ad = Extracts (As, IM16
433
Ad = Extractz (As, IM16
433
Ad = Insert (As, Arm
434
Ad = Insert (As, IM16
435
Ad = as : Aat
436
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