Timing Action With Wait-States - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
External Memory Interface
6.3 Functional Timing
6.3.1 Timing Action with Wait-States (continued)
For a Write cycle:
A one instruction cycle dead zone always precedes the write cycle because all write instructions take a minimum of
two instruction cycles.
Beginning of memory cycle:

CKO goes low.

The data bus is 3-stated.

Either one of the external memory enables goes low, or the leading edge can be delayed one-half a CKO period
by programming a bit in the ioc.

Address bus becomes valid.

RWN goes low.
Midcycle:

CKO goes low for an odd number of wait-states, i.e., high for an even number of wait-states.

The DSP places valid data on the data bus.
End of cycle:

CKO goes low.

RWN goes high.

The selected enable goes high, but can stay low if enabled for the next external memory cycle.

The address bus changes if another external memory cycle starts next. Otherwise, the last valid external
address is held.

The data bus is held valid for one more CKO period unless an external read immediately follows in which case
the bus will be 3-stated.
6-16
(continued)
DRAFT COPY
Information Manual
April 1998
Lucent Technologies Inc.