The Instruction Register-Jir; Figure 11-4.The Jtag Instruction Register/Decoder Structure - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
11.3 Elements of the JTAG Test Logic
11.3.3 The Instruction Register—JIR
The JTAG instruction register (JIR) is a 4-bit scannable shift register with a parallel output stage. The parallel out-
put stage is loaded from the shift register stage in the Update-IR state of the TAP Controller on the falling edge of
TCK. The parallel outputs of JIR provide the currently active instruction to the decoder block that generates regis-
ter enable signals. The serial input of JIR is tied to the TDI pin. The serial output feeds the JOUT block that
chooses between the JIR and the selected TDR depending on whether the TAP Controller is in an IR-scan cycle or
a DR-scan cycle.
All four cells of JIR have the capability of loading the shift register stage from the parallel inputs. The standard
requires cells 0 and 1 to capture constant logic values 1 and 0, respectively, as shown in
UPDATE-IR
TDI
TCK
CAPTURE-IR
SHIFT-IR
The IEEE standard defines the most significant bit (MSB) of each register to be the one closest to the TDI pin and the least significant
Note:
bit (LSB) to be the one closest to the TDO pin. According to this definition, the data should be shifted in LSB first if shifting data into a
register through TDI.
Figure 11-4. The JTAG Instruction Register/Decoder Structure
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
(continued)
INSTRUCTION DECODER
PARALLEL OUTPUT STAGE
CELL 3 CELL 2
PINT JINT
PARALLEL INPUTS
DRAFT COPY
JTAG Test Access Port
REGISTER
ENABLE AND
CONTROL SIGNALS
CELL 1 CELL 0
TO JOUT BLOCK
0 1
Figure 11-4.
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11-7