Control Registers; Table 5-3. Arithmetic Unit Control (Auc) Register - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
5.1 Data Arithmetic Unit

5.1.7 Control Registers

In addition to the registers already mentioned, the user has access to the arithmetic unit control register (auc) and
the processor status word register (psw). The auc register configures some features of the data arithmetic unit as
described in Table 5-3. The auc register is cleared to all zeros at reset. Bits 11 and 10 of the psw are cleared at
reset.

Table 5-3. Arithmetic Unit Control (auc) Register

Bit 15—9
Field
reserved
Field Value
reserved —
RAND 0
1
X=Y= 0
1
CLR 1xx
x1x
xx1
SAT 1x
x1
ALIGN 00
01
10
11
† The auc is a 16 bit register of which 9 bits [8:0] are used for control. The unused upper 7 bits [15:9] are always zero if read and should always
be written with zeros to make the program compatible with future chip versions. The auc register is cleared at reset.
The psw register contains status information from the data arithmetic unit as shown in
is normally read to get status information. However, if it is overwritten, the new information will be considered valid.
Note: There is no capability to write just one or a few bits; all 16 bits have to be written.
psw bits 9 and 4 are ones if a 32-bit overflow occurs from an accumulator calculation for a0 and a1, respectively.
A 32-bit overflow or mathematical overflow occurs if the result of a DAU add/subtract or BMU shift operation cannot
be properly expressed in 32 bits (the sign bit rolls over into bit 33). The accumulator guard bits will then differ from
the sign bit (bit 31). Also, a logical overflow can be detected in the psw register on bit 13 (LLV). A logical overflow
occurs if a number cannot be expressed in 36 bits (36-bit overflow). This can happen if any significant bits are lost
after adding, subtracting, or shifting overflow numbers.
The psw register contains the status of two additional DAU flags: LEQ and LMI. The LEQ (psw[14]) bit is set if the
last DAU/BMU operation produces a result of zero (all 36 bits in the accumulator can be zero). The LMI (psw[15])
bit is set if the last DAU/BMU operation produces a negative number as determined by accumulator bit 35. If bit 35
equals one, the result is negative; but if bit 35 equals zero, the result is positive.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
(continued)
8 7
RAND X=Y=
†
Reserved
Pseudorandom sequence generator (PSG) reset by writing the pi register only
outside an interrupt service routine.
PSG never reset by writing the pi register.
Normal operation.
y = Y transfer statements load both the x and the y registers, allowing single
cycle squaring with p = x * y.
Clearing yl is disabled (enabled if 0).
Clearing a1l is disabled (enabled if 0).
Clearing a0l is disabled (enabled if 0).
a1 saturation on overflow is disabled (enabled if 0).
a0 saturation on overflow is disabled (enabled if 0).
a0, a1 ← p.
a0, a1 ← p/4.
a0, a1 ← p x 4 (and zeros written to the two LSBs).
a0, a1 ← p x 2 (and zeros written to the two LSBs).
DRAFT COPY
6—4 3—2
CLR SAT
Description
Table
Core Architecture
1—0
ALIGN
5-4. The psw register
5-9