DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Instruction Set
4.5 Instruction Set
4.5.4 Special Function Group (continued)
Table 4-10. Special Function Statements
Statement F2
aD = aS >> 1
Arithmetic right shift (sign preserved) of 36-bit accumulators.
aD = aS >> 4
aD = aS >> 8
aD = aS >> 16
aD = aS
36-bit transfer.
aD = –aS
Two's complement.
aD = ~aS
One's complement.
aD = rnd(aS)
Round upper 20 bits of accumulator.
aDh = aSh + 1
Increment high half of accumulator (lower half cleared).
aD = aS + 1
Increment accumulator.
aD = y
32-bit transfer, sign extend into guard bits 35—32.
aD = p
aD = aS << 1
Arithmetic left shift (sign-extended from new bit 31) of the least significant.
aD = aS << 4
32 bits of the 36-bit accumulators.
aD = aS << 8
aD = aS << 16
Table 4-11. Replacement Table for Special Function Instructions
Replace
aD, aS
a0, a1
CON
mi, pl, eq, ne, gt, le, lvc, lvs, mvs, mvc, c0ge, c0lt,
c1ge, c1lt, heads, tails, true, false, allt, allf, somet,
somef, oddp, evenp, mns1, nmns1, npint, njint,
†
lock
, ebusy
† DSP1627/28/29 only.
‡ DSP1618/28 only.
4-20
(continued)
Value
‡
DRAFT COPY
Description
Meaning
One of two DAU accumulators.
See
Table 4-3
cessor flags.
Information Manual
April 1998
for definitions of pro-
Lucent Technologies Inc.