Ad = As Op P - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Instruction Set Summary

aD = aS OP p

(accumulator arithmetic with p register)
(aD) ← (aS) + (p)
(aD) ← (aS) – (p)
(aD) ← (aS) & (p)
(aD) ← (aS) | (p)
(aD) ← (aS) ^ (p)
(aS) – (p)
(aS) & (p)
The specified arithmetic/logical operation OP is performed on the source accumulator aS and the p register (sign-
extended to 36 bits), and the result is placed in aD.
aD = aS + p
aD = aS – p
aD = aS & p
aD = aS | p
aD = aS ^ p
aS – p
aS & p
The F3 field specifies the operation to be performed. The following table provides the encoding for the F3 field:
F3 Field Operation
1000 aD = aS | p
1001 aD = aS ^ p
1010 aS & p
1011 aS – p
1101 aD = aS + p
1110 aD = aS & p
1111 aD = aS – p
others Reserved
Bit 15 14
Field 1 1
Note: The instructions aD = aS + p and aD = aS – p are identical in function to the equivalent F1 operations. By
default, the assembler will produce the F1 encodings for these instructions. To force the (F3) encoding, the
optional mnemonic f3 may be used, as in: f3 a0 = a1 – p
B-43
is a 36-bit add operation writing a 36-bit result.
is a 36-bit subtract operation writing a 36-bit result.
is a 36-bit logical AND operation writing a 36-bit result.
is a 36-bit logical OR operation writing a 36-bit result.
is a 36-bit logical XOR operation writing a 36-bit result.
sets the flags on a 36-bit subtract. No result is written.
sets the flags on a 36-bit logical AND. No result is written.
13 12 11 10
0 0 0 D
Words: 1
Cycles: 1
Group: ALU
Addressing: Register
Flags affected: LMI, LEQ, LLV, LMV
Interruptible: Yes
Cacheable: Yes
Format: 3a
DRAFT COPY
9 8—5
S F3
Information Manual
April 1998
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